Timer Bi Interrupt Control Register - Renesas 7700 FAMILY User Manual

TIMER B
6.2 Block description

6.2.4 Timer Bi interrupt control register

Figure 6.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer
to "Chapter 4. INTERRUPTS."
b7 b6 b5 b4 b3 b2
Fig. 6.2.4 Structure of timer Bi interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits select a timer Bi interrupt's priority level. When using timer Bi interrupts, select priority
levels 1 to 7. When the timer Bi interrupt request occurs, its priority level is compared with the
processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority
level is higher than the IPL. (However, this applies when the interrupt disable bit (I) = "0.") To disable
timer Bi interrupts, set these bits to "000
(2) Interrupt request bit (bit 3)
This bit is set to "1" when the timer Bi interrupt request occurs. This bit is automatically cleared to
"0" when the timer Bi interrupt request is accepted. This bit can be set to "1" or cleared to "0" by
software.
6–6
b1 b0
Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A
Bit
Interrupt priority level select bits
0
1
2
Interrupt request bit
3
7 to 4 Nothing is assigned.
7751 Group User's Manual
Bit name
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : No interrupt request
1 : Interrupt request
" (level 0).
2
to 7C )
16 16
Functions
At reset
0
Low level
0
0
High level
0
Undefined
RW
RW
RW
RW
RW
–