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8.2.3 A-D register i (i = 0 to 7)
Figure 8.2.4 shows the structure of the A-D register i. When the A-D conversion is completed, the conversion
result (contents of the successive approximation register) is stored into this register. Each A-D register i
corresponds to an analog input pin (AN
A-D register i.
8-bit mode
(b15)
b7
10-bit mode
(b15)
(b10)
b7
b2
Fig. 8.2.4 Structure of A-D register i
). Table 8.2.2 lists the correspondence of an analog input pin to
i
(b8)
b0
b7
(b8)
b0
b7
7751 Group User's Manual
A-D CONVERTER
A-D register 0 (Addresses 21
A-D register 1 (Addresses 23
A-D register 2 (Addresses 25
A-D register 3 (Addresses 27
b0
A-D register 4 (Addresses 29
A-D register 5 (Addresses 2B
A-D register 6 (Addresses 2D
A-D register 7 (Addresses 2F
Functions
Bit
Reads an A-D conversion result.
7 to 0
15 to 8 The value is "0" at reading.
A-D register 0 (Addresses 21
A-D register 1 (Addresses 23
A-D register 2 (Addresses 25
A-D register 3 (Addresses 27
b0
A-D register 4 (Addresses 29
A-D register 5 (Addresses 2B
A-D register 6 (Addresses 2D
A-D register 7 (Addresses 2F
Functions
Bit
Reads an A-D conversion result.
9 to 0
The value is "0" at reading.
15 to 10
Table 8.2.2 Correspondence of analog input pin
and A-D register i
Analog input pin
AN
pin
0
AN
pin
1
AN
pin
2
AN
pin
3
AN
pin
4
AN
pin
5
AN
pin
6
AN
pin
7
8.2 Block description
, 20
)
16
16
, 22
)
16
16
, 24
)
16
16
, 26
)
16
16
, 28
)
16
16
, 2A
)
16
16
, 2C
)
16
16
, 2E
)
16
16
At reset
RW
RO
Undefined
RO
0
, 20
)
16
16
, 22
)
16
16
, 24
)
16
16
, 26
)
16
16
, 28
)
16
16
, 2A
)
16
16
, 2C
)
16
16
, 2E
)
16
16
RW
At reset
RO
Undefined
RO
0
A-D register i where
conversion result is stored
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
8–7
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