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External data bus width = 8 bits (BYTE = "H")
E
ALE
Port P0
(A
–A
)
0
7
Port P1
(A
–A
)
8
15
Port P2
(A
/D
–A
/D
)
16
0
23
7
R/W
External data bus width = 16 bits (BYTE = "L")
E
ALE
Port P0
(A
–A
)
0
7
Port P1
(A
/D
–A
/D
)
8
8
15
15
Port P2
(A
/D
–A
/D
)
16
0
23
7
R/W
Fig. 17.1.1 Bus timing diagrams
t
w(EL)
Address low-order
Address middle-order
External memory
Address
output data
high-order
t
a(AD)
t
su(P0A/P1A/P2A–P1D/P2D)
When reading data
t
w(EL)
Address low-order
Address
External memory
middle-order
output data
External memory
Address
output data
high-order
t
a(AD)
t
SU(P0A/P1A/P2A-P1D/P2D)
When reading data
7751 Group User's Manual
APPLICATIONS
17.1 Memory expansion
t
w(EL)
Address low-order
Address middle-order
Address
Data
high-order
t
d(E-P2Q)
t
su(D)
When writing data
t
w(EL)
Address low-order
Address
Data (odd address)
middle-order
t
d(E-P1Q)
Address
Data (even address)
high-order
t
d(E-P2Q)
t
su(D)
When writing data
: Specifications of the M37751
(The others are the external memory's.)
17–5
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