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9.1.1 Watchdog timer
Watchdog timer is a 12-bit counter that down-counts the count source which is selected with the watchdog
timer frequency select bit (bit 0 at address 61
in the cases listed below. An arbitrary value cannot be set to Watchdog timer.
When dummy data is written to the watchdog timer register (Refer to Figure 9.1.2.)
When the most significant bit of Watchdog timer becomes "0"
When the STP instruction is executed (Refer to "Chapter 10. STOP MODE.")
At reset
b7
Fig. 9.1.2 Structure of watchdog timer register
b0
Watchdog timer register (Address 60
Bit
7 to 0
Initializes the watchdog timer.
When a dummy data is written to this register, the watchdog
timer's value is initialized to "FFF
7751 Group User's Manual
WATCHDOG TIMER
). A value "FFF
" is automatically set in Watchdog timer
16
16
)
16
Functions
." (Dummy data: 00
16
9.1 Block description
At reset
RW
Undefined
to FF
)
16
16
–
9–3
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