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SERIAL I/O
7.3 Clock synchronous serial I/O mode
7.3.1 Transfer clock (synchronizing clock)
Data transfer is performed synchronously with the transfer clock. For the transfer clock, the user can select
whether to generate the transfer clock internally or to input it from an external.
The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing
only reception, set the transmit enable bit to "1," and set dummy data in the UARTi transmit buffer register
in order to make the transmit control circuit active.
(1) Generating transfer clock internally
The count source selected with the BRG count source select bits is divided by the BRGi, and its
BRGi output is further divided by 2. This is the transfer clock. The transfer clock is output from the
CLK
pin.
i
[Setting relevant registers]
•Select an internal clock (bit 3 at addresses 30
•Select the BRGi's count source (bits 0 and 1 at addresses 34
•Set "divide value – 1" (= n; 00
Transfer clock frequency =
•Enable transmission (bit 0 at addresses 35
•Set data to the UARTi transmit buffer register (addresses 32
[Pin's state]
•A transfer clock is output from the CLK
•Serial data is output from the TxDi pin. (Dummy data is output when performing only reception.)
(2) Inputting transfer clock from an external
A clock input from the CLK
[Setting relevant registers]
•Select an external clock (bit 3 at addresses 30
•Enable transmission (bit 0 at addresses 35
•Set data to the UARTi transmit buffer register (addresses 32
[Pin's state]
•A transfer clock is input from the CLK
•Serial data is output from the TxD
7–18
16
to FF
) to the BRGi (addresses 31
16
16
f
i
f
: Frequency of BRGi's count source (f
2 (n+1)
i
, 3D
16
pin.
i
pin is the transfer clock.
i
16
, 3D
16
pin.
i
pin. (Dummy data is output when performing only reception.)
i
7751 Group User's Manual
, 38
= "0").
16
, 3C
)
16
16
16
= "1").
16
, 3A
)
16
16
, 38
= "1").
16
= "1").
16
, 3A
).
16
16
, 39
).
16
f
, f
f
, f
f
, f
2/
4
16/
32
64/
128
512/
f
)
1024
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