Renesas 7700 FAMILY User Manual page 62

b7 b6 b5 b4 b3 b2
b7 b6 b5 b4 b3 b2 b1
Fig. 4.3.2 Structure of interrupt control register
b1 b0
A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2
interrupt control registers (Addresses 70
Bit
Interrupt priority level select bits
0
1
2
Interrupt request bit
3
7 to 4 Nothing is assigned.
b0
INT to INT interrupt control registers (Addresses 7D
0 2
Bit
Interrupt priority level select bits
0
1
2
Interrupt request bit (Note)
3
4 Polarity select bit
Level sense/Edge sense select
5
bit
Nothing is assigned.
7, 6
Note: The INT to INT
0
7751 Group User's Manual
to 7C )
16 16
Bit name
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : No interrupt request
1 : Interrupt request
Bit name
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : No interrupt request
1 : Interrupt request
0 : Set the interrupt request bit at
"H" level for level sense and at
falling edge for edge sense.
1 : Set the interrupt request bit at
"L" level for level sense and at
rising edge for edge sense.
0 : Edge sense
1 : Level sense
interrupt request bits are invalid when selecting the level sense.
2
INTERRUPTS
4.3 Interrupt control
Functions
At reset
0
Low level
0
0
High level
0
Undefined
to 7F )
16 16
Functions
At reset
0
Low level
0
0
High level
0
0
0
Undefined
RW
RW
RW
RW
RW
–
RW
RW
RW
RW
RW
RW
RW
–
4–7