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CONNECTION WITH EXTERNAL DEVICES
Table 12.2.2 Bus cycle
Low-speed running [ f (X
Internal area access
(Note)
2 access in
low-speed running
1 bus cycle = 2
E
ALE
Reading
A
A W
Writing
Note : Signals when accessing an internal area means signals which are output from pins
externally when accessing an internal area in the memory expansion mode.
A: Address
R: Data to be read
) ≤ 25 MHz ]
IN
External area access
2 access in
low-speed running
1 bus cycle = 2
E
ALE
Reading
A
R
A W
Writing
3 access in
low-speed running
1 bus cycle = 3
E
ALE
Reading
A
R
Writing
A
W
4 access in
low-speed running
1 bus cycle = 4
E
Reading
A
R
Writing
A
W
W: Data to be written
?: Undefined value
7751 Group User's Manual
High-speed running [ f (X
Internal area access
(Note)
2 access in
high-speed running
(RAM)
1 bus cycle = 2
E
ALE
Reading
A
Writing
A
?
3 access in high-speed
running (ROM, SFR)
1 bus cycle = 3
E
ALE
Reading
A
Writing
A
W
12.2 Bus cycle
) ≤ 40 MHz ]
IN
External area access
3 access in high-speed
running
1 bus cycle = 3
E
ALE
Reading
A
R
Writing
A
W
4 access in high-speed running
1 bus cycle = 4
E
E
ALE
ALE
Reading
Reading
A
A
R
R
Writing
Writing
A
A
W
W
5 access in high-speed running
1 bus cycle = 5
E
ALE
Reading
Reading
A
A
Writing
Writing
A
A
W
W
R
R
12–13
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