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FLASH MEMORY VERSION
19.1 Parallel input/output mode
Program command
Figure 19.1.6 shows the program command and the program verify command execution timing.
The command code is latched into the internal command latch at the rising edge of the WE signal
by inputting the control signals and the command code "40
The address is latched into the internal at the falling edge of the WE signal and the data is latched
at the rising edge of the WE signal by inputting the address, data, and control signals in the
second cycle.
The program is started at the rising edge of the WE signal in the second cycle and the input data
is programmed to the specified address (input address) within 10 µ s as measured by its internal
timer. Programming is performed by the byte unit.
Note: Be sure to execute a program verify command after executing the program command. If this
verification fails, execute repeatedly the program command and the program verify command
until the verification passes. (Refer to "19.1.6 Program/erase algorithm flow chart.")
Program verify command
This command is executed to verify the program data after executing the program command.
The command code is latched into the internal command latch at the rising edge of the WE signal
by inputting the control signals and the command code "C0
The data of the address where the program command is executed is output to an external by
inputting the control signals in the second cycle.
Since the address is internally latched when the program command is executed, there is no need
to input it when the program verify command is executed.
19–12
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7751 Group User's Manual
" in the first cycle.
16
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" in the first cycle.
16
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