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CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
(2) External data bus width switching signal (BYTE pin level)
This signal is used to select the external data bus width between 8 bits and 16 bits. When this signal
level is "L," the external data bus width is 16 bits; when the level is "H," the bus width is 8 bits (refer
to Table 12.1.1.)
Fix this signal to either "H" or "L" level.
This signal is valid only for the external areas. When accessing the internal areas, the data bus width
is always 16 bits.
(3)
Enable signal (E)
This signal becomes "L" level while reading or writing data to and from the data bus. (See Table
12.1.2.)
(4)
Read/Write signal (R/W)
This signal indicates the state of the data bus. This signal becomes "L" level while writing to the data
bus. Table 12.1.2 lists the state of the data bus indicated with the E and R/W signals.
(5)
Byte high enable signal (BHE)
This signal indicates the access to an odd address. This signal becomes "L" level when accessing
an only odd address or when simultaneously accessing odd and even addresses.
This signal is used to connect memories or I/O devices of which data bus width is 8 bits when the
external data bus width is 16 bits.
Table 12.1.3 lists levels of the external address bus A
Table 12.1.3 Levels of A
Access address
A
0
____
BHE
(6) Address latch enable signal (ALE)
This signal is used to obtain the address from the multiplexed signal of address and data that is input
and output to and from the A
is "H," latch the address and simultaneously output the addresses. When this signal is "L," retain the
latched address.
(7)
Ready function-related signal (
This is the signal to use the Ready function. (Refer to section "12.3 Ready function.")
(8)
Hold function-related signals (
These are the signals to use the Hold function. (Refer to section "12.4 Hold function.")
12–6
__
__
____
____
and BHE signal and access addresses
0
Even and odd addresses
(Simultaneous 2-byte access)
L
L
/D
to A
8
8
15
____
)
RDY
_____
HOLD
7751 Group User's Manual
Table 12.1.2 State of data bus indicated with E
_
E
H
L
and the
0
Even address
(1-byte access)
L
H
/D
and A
/D
to A
/D
15
16
0
23
_____
,
)
HLDA
_
__
__
and R/W signals
__
R/W
State of data bus
H
Not used
L
H
Read data
L
Write data
____
signal and access addresses.
BHE
Odd address
(1-byte access)
pins. Make sure that when this signal
7
_
H
L
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