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M37751
A
–A
8
23
(D
–D
)
0
15
A
–A
0
7
RDY
E
AC04
1
1
1
E
1Q (AC74)
2Q (AC74)
CS
2
RDY
Ready request is accepted at the RDY pin input level judgment timing A .
Ready state release request is accepted at the RDY pin input level judgment timing B .
Fig. 17.1.9 Example of using Ready function (at 3 φ access in low–speed running)
Address
Address
decode
latch circuit
circuit
AC04
1D
CLR
1Q
2D
2Q
1T
2T
1
AC74
1
) ≤ 25 MHz, 3 access in low–speed running
Circuit condition: f(X
IN
t
d
(E-φ
)
1
t
su(RDY-
)
1
Sum of propagation delay time for AC32 , AC74,
and AC04(max. : 26 ns)
7751 Group User's Manual
1 to 3
Use the elements of which sum of
Data bus
propagation delay time is within
9
2
10
CS
1
f(X
)
IN
(f(X
) = 25 MHz, 40 ns).
IN
CS
2
Address bus
3
AC32
Ready function is available
only for areas accessed
by CS
.
2
2
A
B
t
c
t
su(RDY-
)
1
APPLICATIONS
17.1 Memory expansion
–t
(RDY–
)
su
1
: E ( "L" level) stop by Ready function.
17–13
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