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STOP MODE
10.1 Clock generating circuit
This chapter describes Stop mode.
Stop mode is used to stop oscillation when there is no need to operate the central processing unit (CPU).
The microcomputer enters Stop mode when the STP instruction is executed.
Stop mode can be terminated by an interrupt request occurrence or the hardware reset.
10.1 Clock generating circuit
Figure 10.1.1 shows the clock generating circuit.
Interrupt request
S
STP instruction
R
Reset
S
R
S
WIT instruction
R
Clock source for peripheral devices select bit : Bit 2 at address 5F
Watchdog timer frequency select bit : Bit 0 at address 61
CPU : Central processing unit
BIU : Bus interface unit
Note: This is the signal generated when the watchdog timer's most significant bit becomes "0."
Fig. 10.1.1 Clock generating circuit
10–2
Clock source for
X
X
IN
OUT
1
peripheral devices
select bit
1/2
1/2
Q
Hold request
Q
Ready request
Request of CPU wait
Q
from BIU
7751 Group User's Manual
1/8
1/4
1/8
0
1
1/16
1/16
BIU
CPU
16
16
f
/f
2
4
f
/f
16
32
Operation clock for
internal peripheral devices
f
/f
64
128
f
/f
512
1024
Wf
/Wf
64 1
32
Watchdog
Wf
/Wf
timer
512
1024
0
Watchdog timer frequency
select bit
(Note)
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