Renesas 7700 FAMILY User Manual page 281

CONNECTION WITH EXTERNAL DEVICES
12.3 Ready function
2 access in low-speed running, 2 access in high-speed running
Judgment timing of input level to RDY pin
3 access in low-speed running, 3 access in high-speed running
Judgment timing of input level to RDY pin
Fig. 12.3.1 Timings of acceptance of Ready request and termination of Ready state (1)
12–16
Clock
1
BIU
CPU
E
ALE
RDY
Term unusing bus
Clock
1
BIU
CPU
E
Low-speed 3
ALE
RDY
By accepting an Ready request, "L" level of
by , and clocks and
BIU
Ready state is terminated.
Input level to the pin is not judged during the term unusing the bus or before the condition
RDY
above .
Notes 1: The timing of ALE signal differs depending on low-speed running or high-speed running,
and accessing an internal area or an external area. For more information, refer to section
"Chapter 15. ELECTRICAL CHARACTERISTICS ."
2: The dotted lines of signals
pin is "H", no Ready request.
RDY
3: In high-speed running, the internal RAM is accessed by 2 access in high-speed running.
7751 Group User's Manual
High-speed 2
Low-speed 2
Term using bus
High-speed 3
Term using bus
signal stops for 1 cycle with the clock
E
stop at "L" level.
CPU
, and indicate the waveform when input level to the
E
BIU CPU
, indicated
1