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Address
0
16
1
16
Port P0 register
2
16
3
Port P1 register
16
Port P0 direction register
4
16
5
Port P1 direction register
16
Port P2 register
6
16
7
Port P3 register
16
Port P2 direction register
8
16
9
Port P3 direction register
16
Port P4 register
A
16
B
Port P5 register
16
C
Port P4 direction register
16
D
Port P5 direction register
16
E
Port P6 register
16
Port P7 register
F
16
Port P6 direction register
10
16
11
Port P7 direction register
16
Port P8 register
12
16
13
16
Port P8 direction register
14
16
15
16
16
16
17
16
18
16
19
16
1A
16
1B
16
1C
16
1D
16
A-D control register 0
1E
16
1F
A-D control register 1
16
20
16
A-D register 0
21
16
22
16
A-D register 1
23
16
24
16
A-D register 2
25
16
26
16
A-D register 3
27
16
28
16
A-D register 4
29
16
2A
16
A-D register 5
2B
16
2C
16
A-D register 6
2D
16
2E
16
A-D register 7
2F
16
30
UART0 transmit/receive mode register
16
31
UART0 baud rate register (BRG0)
16
32
16
UART0 transmit buffer register
33
16
34
UART0 transmit/receive control register 0
16
35
UART0 transmit/receive control register 1
16
36
16
UART0 receive buffer register
37
16
38
UART1 transmit/receive mode register
16
39
UART1 baud rate register (BRG1)
16
3A
16
UART1 transmit buffer register
3B
16
3C
UART1 transmit/receive control register 0
16
3D
UART1 transmit/receive control register 1
16
3E
16
UART1 receive buffer register
3F
16
Fig. 2.4.2 SFR area's memory map
CENTRAL PROCESSING UNIT (CPU)
7751 Group User's Manual
2.4 Memory assignment
Address
Count start register
40
16
41
16
42
One-shot start register
16
43
16
Up-down register
44
16
45
16
46
16
Timer A0 register
47
16
48
16
Timer A1 register
49
16
4A
16
Timer A2 register
4B
16
4C
16
Timer A3 register
4D
16
4E
16
Timer A4 register
4F
16
50
16
Timer B0 register
51
16
52
16
Timer B1 register
53
16
54
16
Timer B2 register
55
16
Timer A0 mode register
56
16
57
Timer A1 mode register
16
Timer A2 mode register
58
16
59
Timer A3 mode register
16
5A
Timer A4 mode register
16
5B
Timer B0 mode register
16
Timer B1 mode register
5C
16
5D
Timer B2 mode register
16
Processor mode register 0
5E
16
5F
Processor mode register 1
16
60
Watchdog timer register
16
61
Watchdog timer frequency select register
16
62
16
63
16
64
16
65
16
66
16
67
16
68
16
69
16
6A
16
6B
16
6C
16
6D
16
6E
16
6F
16
70
A-D conversion interrupt control register
16
71
UART0 transmit interrupt control register
16
72
UART0 receive interrupt control register
16
73
UART1 transmit interrupt control register
16
74
UART1 receive interrupt control register
16
75
16
Timer A0 interrupt control register
76
Timer A1 interrupt control register
16
77
16
Timer A2 interrupt control register
78
Timer A3 interrupt control register
16
79
16
Timer A4 interrupt control register
7A
Timer B0 interrupt control register
16
7B
16
Timer B1 interrupt control register
7C
Timer B2 interrupt control register
16
7D
interrupt control register
16
INT
0
7E
interrupt control register
INT
16
1
7F
16
INT
interrupt control register
2
2–21
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