Renesas 7700 FAMILY User Manual page 39

CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
000000
16
00007F
16
000080
16
00087F
16
004000
16
00FFD6
16
00FFFF
16
M37751M6C-XXXFP
: The internal memory is not assigned.
Notes 1:
DBC
2: Access to the internal ROM area is disabled in the microprocessor mode.
(Refer to section "2.5 Processor modes." )
3: Memory assignment of internal area varies according to the type of microcomputer.
Refer to "Appendix 1. Memory assignment" for other products.
Fig. 2.4.1 Internal area's memory assignment
2–20
SFR area
Internal RAM area
Internal ROM area
is an interrupt only for debugging; do not use this interrupt.
7751 Group User's Manual
Refer to Figure 2.4.2.
FFD6
16
FFD8
16
FFDA
16
FFDC
16
FFDE
16
FFE0
16
FFE2
16
FFE4
16
FFE6
16
FFE8
16
FFEA
16
FFEC
16
FFEE
16
FFF0
16
FFF2
16
FFF4
16
FFF6
16
FFF8
16
FFFA
16
FFFC
16
FFFE
16
Interrupt vector table
L
A-D conversion
H
L
UART1 transmit
H
L
UART1 receive
H
L
UART0 transmit
H
L
UART0 receive
H
L
Timer B2
H
L
Timer B1
H
L
Timer B0
H
L
Timer A4
H
L
Timer A3
H
L
Timer A2
H
L
Timer A1
H
L
Timer A0
H
L
INT
2
H
L
INT
1
H
L
INT
0
H
L
Watchdog timer
H
L
DBC (Note 1)
H
L
BRK instruction
H
L
zero divide
H
L
RESET
H