Renesas 7700 FAMILY User Manual page 207

SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
BRGi count
source
"1"
Receive enable bit
"0"
RxD
i
Transfer clock
"1"
Receive
complete flag
"0"
"H"
RTS
i
"L"
"1"
UARTi receive interrupt
request bit
"0"
Fig. 7.4.11 Example of receive timing when transfer data length is 8 bits (when parity disabled,
selecting 1 stop bit)
7–50
Start bit
Sampled "L"
Reception started at falling of start bit
The above timinig diagram applies to
the following conditions:
Parity disabled
1 stop bit
RTS function selected
7751 Group User's Manual
D D
D
1
0
Receive data taken in
UARTi receive register
Cleared to "0" when interrupt request is accepted
or cleared by software.
Stop bit
7
UARTi receive buffer register