Pin State - Renesas 7700 FAMILY User Manual

13.1.1 Pin state

Table 13.1.1 lists the microcomputer's pin state while the RESET pin is "L" level.
Table 13.1.1 Pin state while
Mask ROM version
PROM version
(Including One time PROM
and EPROM versions)
Flash memory version
Notes 1: Each pin becomes the above state. It is because the microcomputer enters the EPROM mode.
Refer to "Chapter 18. PROM VERSION."
2: Each pin becomes the above state. It is because the microcomputer enters the Flash memory
mode. Refer to "Chapter 19. FLASH MEMORY VERSION."
______
pin is "L" level
RESET
CNV pin level Pin (Port) name
SS
Vss or Vcc P0 to P8
_
E
Vss P0 to P8
_
E
Vcc (Note 1) P0, P1, P3 to P8
P2
_
E
P0 to P8
Vss
_
E
P0, P1, P3 to P8
Vcc (Note 2)
P2
_
E
P0, P1, P3, P4
V H (Note 2)
PP
P4 , P4
1
P5 to P8
P2
P4
2
P4
4
_
E
7751 Group User's Manual
______
Floating.
Outputs "H" level.
Floating.
Outputs "H" level.
Floating.
Floating while supplying "H" level
to two pins of P5
of them.
Outputs "H" or "L" level while sup-
plying "L" level to two pins of P5
and P5
Outputs "H" level.
Floating.
Outputs "H" level.
Floating.
Floating while supplying "H" level
to two pins of P5
of them.
Outputs "H" or "L" level while sup-
plying "L" level to two pins of P5
and P5
Outputs "H" level.
Floating.
,
0
,P4 to P4 ,
3 5 7
Floating while supplying "H" level
to two pins of P5
of them.
Outputs "H" or "L" level while sup-
plying "L" level to two pins of P5
and P5
Outputs clock φ
Floating while supplying "L" level to
one or more pins of P4
Outputs "H" or "L" level while sup-
plying "H" level to three pins of P4
P4 and P5
6
Outputs "H" level.
RESET
13.1 Hardware reset
Pin state
and P5 , or one
1 2
.
2
and P5 , or one
1 2
.
2
and P5 , or one
1 2
.
2
.
1
, P4 and P5
5 6
.
1
1
1
1
.
1
,
5
13–3