Clock Generated In Clock Generating Circuit - Renesas 7700 FAMILY User Manual

CLOCK GENERATING CIRCUIT
14.2 Clock

14.2.1 Clock generated in clock generating circuit

(1) φ
This is the clock source of φ
(2) φ
CPU
This is the operation clock of CPU.
(3) φ
BIU
This is the operation clock of BIU.
(4) Clock φ
1
This has the same period as φ and is output to the external.
(5) f /f to f /f
2 4 512 1024
Each of them is the operation clock for the
internal peripheral devices, and its clock source
is φ or φ divided by 2.
(Refer to "14.2.2 Operation clock for internal
peripheral devices.")
(6) Wf /Wf , Wf
32 64 512
This is the operation clock of Watchdog timer,
and its clock source is φ or φ divided by 2.
(Refer to "14.2.2 Operation clock for internal
peripheral devices.")
14–4
, φ
CPU BIU
/Wf
1024
7751 Group User's Manual
clock φ
, f /f to f /f
1 2 4 512 1024
Table 14.2.1 Operation clock for internal peripheral devices
Operation clock
f /f
2 4
f /f
16 32
f /f
64 128
f /f
512 1024
Table 14.2.2 Operation clock for Watchdog timer
Operation clock
Wf /Wf
32 64
Wf /Wf
512 1024
, Wf /Wf and Wf /Wf
32 64 512
Clock source for peripheral
devices select bit (See Fig. 14.2.2)
1
f
2
f
16
f
64
f
512
Clock source for peripheral
devices select bit (See Fig. 14.2.2)
1
Wf
32
Wf
512
.
1024
0
f
4
f
32
f
128
f
1024
0
Wf
64
Wf
1024