Renesas 7700 FAMILY User Manual page 182

Transfer clock
Fig. 7.3.4 Transmit operation
Transfer clock
"1"
Transmit enable bit
"0"
"1"
Transmit buffer
empty flag
"0"
"H"
CTS
i
"L"
CLK
i
T
i
END
TxD
i
"1"
Transmit register
empty flag
"0"
"1"
UARTi transmit
interrupt request bit
"0"
The above timing diagram applies to
the following conditions:
Internal clock selected
CTS function selected.
Fig. 7.3.5 Example of transmit timing (when selecting internal clock)
UARTi transmit buffer register
UARTi transmit register
Tc
Data is set in UARTi transmit buffer register.
UARTi transmit register
T
CLK
Stopped because CTSi = "H."
D D D D D D D D
0 1 2 3 4 5 6 7
Cleared to "0" when interrupt request is accepted or cleared by software.
T : Next transmit conditions are examined when this signal level is "H."
ENDi
(T
ENDi
Tc = T = 2(n+1) /fi
CLK
fi: BRGi count source frequency (f
n: Value set to BRGi
7751 Group User's Manual
7.3 Clock synchronous serial I/O mode
b7
Transmit data
MSB
D D D
7 6 5
D D
7 6
D
7
UARTi transmit buffer register.
D D D D D D D D
0 1 2 3 4 5 6 7
is an internal signal. Accordingly, it cannot be read from an external.)
/f , f /f , f
2 4 16 32 64
SERIAL I/O
b0
LSB
D D D D D
4 3 2 1 0
D D D D D
5 4 3 2 1
D D D D D
6 5 4 3 2
D D D D D
7 6 5 4 3
Stopped because transmit enable bit = "0."
D D D D D D D
0 1 2 3 4 5 6
/f , f /f )
128 512 1024
D
0
D
1
D
2
D
7
D
7
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