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(1) Internal/External clock select bit (bit 3)
[Clock synchronous serial I/O mode]
By clearing this bit to "0" in order to select an internal clock, the clock which is selected with the
BRG count source select bits (bits 0 and 1 at addresses 34
BRGi (described later). The BRGi output of which frequency is divided by 2 becomes the transfer
clock. Additionally, the transfer clock is output from the CLK
By setting this bit to "1" in order to select an external clock, the clock input to the CLK
becomes the transfer clock.
[UART mode]
By clearing this bit to "0" in order to select an internal clock, the clock which is selected with the
BRG count source select bits (bits 0 and 1 at addresses 34
the BRGi (described later). Then, the CLK
By setting this bit to "1" in order to select an external clock, the clock input to the CLK
becomes the count source of BRGi.
Always in the UART mode, the BRGi output of which frequency is divided by 16 is the transfer
clock.
pin functions as a programmable I/O port.
i
7751 Group User's Manual
SERIAL I/O
7.2 Block description
, 3C
) becomes the count source of
16
16
pin.
i
, 3C
) becomes the count source of
16
16
pin
i
pin
i
7–5
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