Renesas 7700 FAMILY User Manual page 531

APPENDIX
Appendix 9. Q & A
Q
Is there any precaution when f(X
A
Set the processor mode register 1 (address 5F
b7
0 0
The microcomputer becomes the following state by the setting above.
f , f , f , or f
4 32 128
as timer.
SFR and internal ROM area are accessed at 3 φ bus cycle. Internal RAM area is accessed
at 2 φ bus cycle.
3 φ , 4 φ , or 5 φ can be selected for the bus cycle when accessing an external device. 2 φ cannot
be selected for the bus cycle.
20–80
) > 25 MHz ?
IN
b0
0 0
0 0
Fix these bits to "0."
Bus cycle when accessing external device
b5 b4
0 0 : 5 φ
0 1 : 4 φ
1 0 : 3 φ
(1 1: Not selected)
Fix these bits to "0."
can be selected for the operating clock of internal peripheral devices such
1024
7751 Group User's Manual
) to the following.
16
Clock