Termination By Interrupt Request Occurrence - Renesas 7700 FAMILY User Manual

STOP MODE
10.2 Operation description

10.2.1 Termination by interrupt request occurrence

When terminating Stop mode by interrupt request occurrence, instructions are executed after a certain time
measured by the watchdog timer has passed.
When an interrupt request occurs, the oscillator starts oscillating. Simultaneously, supply of , clock φ
f /f to f /f , Wf
2 4 512 1024
The watchdog timer starts counting owing to the oscillation start. The watchdog timer counts Wf
When the watchdog timer's MSB becomes "0," supply of φ
timer's count source returns to Wf
select bit (bit 0 at address 61
The interrupt request which occurs in
Table 10.2.2 lists the interrupts used to terminate Stop mode.
Table 10.2.2 Interrupts used to terminate Stop mode
Interrupt
____
interrupt (i = 0 to 2)
INT
i
Timer Ai interrupt (i = 0 to 4)
Timer Bi interrupt (i = 0 to 2)
UARTi transmit interrupt (i = 0, 1)
UARTi receive interrupt (i = 0, 1)
Notes 1: Since the oscillator has stopped oscillating, each function does not work unless they are operated
under the above condition. Also, the A-D converter does not work.
2: Since the oscillator has stopped oscillating, no interrupts other than those above can be used.
3: Refer to "Chapter 4. INTERRUPT" and the description of each internal peripheral device for
details about each interrupt.
Before executing the STP instruction, enable interrupts used to terminate Stop mode.
In addition, the interrupt priority level of the interrupt used to terminate Stop mode must be higher than the
processor interrupt priority level (IPL) of the routine where the STP instruction is executed. When multiple
interrupts in Table 10.2.2 are enabled, Stop mode is terminated by the first interrupt request.
There is possibility that all interrupt requests occur after the oscillation starts in
φ
and starts in . The interrupt requests which occur during this time are accepted in order of priority
BIU
(Note) after the watchdog timer's MSB becomes "0."
For interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled) before
executing the STP instruction.
Note : The interrupt request which has the highest priority is accepted first.
10–4
/Wf , and Wf /Wf
32 64 512 1024
/Wf
32 64
).
16
Conditions for using each function to generate interrupt request
Enabled in event counter mode
Enabled when selecting external clock
7751 Group User's Manual
starts.
, φ
CPU BIU
or Wf /Wf that is selected by the watchdog timer frequency
512 1024
is accepted.
starts. At the same time, the watchdog
and until supply of
φ
,
1
/Wf .
32 64
φ
CPU