Renesas 7700 FAMILY User Manual page 467

APPENDIX
Appendix 3. Control registers
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1
UARTi receive buffer register
(b15)
b7
20–16
b0
UART0 transmit/receive control register 1 (Address 35
UART1 transmit/receive control register 1 (Address 3D
Bit name
Bit
0 Transmit enable bit
1 Transmit buffer empty flag
2 Receive enable bit
3 Receive complete flag
4 Overrun error flag
5 Framing error flag
(Valid in UART mode)
6 Parity error flag
(Valid in UART mode)
7 Error sum flag
(Valid in UART mode)
Notes 1: Bit 4 is cleared to "0" when clearing the receive enable bit to "0."
Bits 5 and 6 are cleared to "0" when one of the following is performed:
•clearing the receive enable bit to "0."
•reading the low-order byte of the UARTi receive buffer register (addresses 36
Bit 7 is cleared to "0" when all of bits 4 to 6 become "0."
2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode.
(b8)
b0 b7
7751 Group User's Manual
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in transmit buffer
register.
1 : No data present in transmit
buffer register.
0 : Reception disabled
1 : Reception enabled
0 : No data present in receive
buffer register.
1 : Data present in receive buffer
register.
0 : No overrun error
(Note 1)
1 : Overrun error detected
(Notes 1, 2)
0 : No framing error
1 : Framing error detected
(Notes 1, 2)
0 : No parity error
1 : Parity error detected
(Notes 1, 2)
0 : No error
1 : Error detected
b0
UART0 receive buffer register (Addresses 37
UART1 receive buffer register (Addresses 3F
Bit Functions
Receive data is read out from here.
8 to 0
Nothing is assigned.
15 to 9
The value is "0" at reading.
)
16
)
16
Functions
At reset
0
1
0
0
0
0
0
0
, 36
16
, 3E
16
At reset
Undefined
RW
RW
RO
RW
RO
RO
RO
RO
RO
, 3E ) out.
16 16
)
16
)
16
RW
RO
–
0