Repeat Sweep Mode 0 Operation Description; Repeat Sweep Mode 1 - Renesas 7700 FAMILY User Manual

Mitsubishi 16-bit single-chip microcomputer
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8.9.2 Repeat sweep mode 0 operation description

(1) When an internal trigger is selected
The A-D converter starts conversion for the input voltage from the AN
conversion start bit is set to "1."
The A-D conversion of the input voltage from the AN
the 8-bit mode, or 59 cycles of φ
approximation register (conversion result) are transferred to the A-D register 0.
The operation to all selected analog input pins is performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
The operation to all selected analog input pins is performed again.
The operation is performed repeatedly until the A-D conversion start bit is cleared to "0" by software.
(2) When an external trigger is selected
The A-D converter starts conversion for the input voltage from the AN
______
the
pin changes from "H" to "L" while the A-D conversion start bit is "1."
AD
TRG
The A-D conversion of the input voltage from the AN
the 8-bit mode, or 59 cycles of φ
approximation register (conversion result) are transferred to the A-D register 0.
The operation to all selected analog input pins is performed.
The conversion result is transferred to the A-D register i each time each pin is converted.
The operation to all selected analog input pins is performed again.
The operation is performed repeatedly until the A-D conversion start bit is cleared to "0" by software.
When the level of the
is cancelled and is restarted from step
Figure 8.9.2 shows the conversion operation in the repeat sweep mode 0.
in the 10-bit mode. Then, the contents of the successive
AD
in the 10-bit mode. Then, the contents of the successive
AD
______
pin changes from "H" to "L" during operation, the operation at that point
AD
TRG
.
7751 Group User's Manual
A-D CONVERTER
8.9 Repeat sweep mode 0
pin starts when the A-D
0
pin is completed after 49 cycles of φ
0
pin when the input level to
0
pin is completed after 49 cycles of φ
0
in
AD
in
AD
8–29

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