Clock - Renesas 7700 FAMILY User Manual

14.2 Clock

Figure 14.2.1 shows the clock generating circuit block diagram.
Interrupt request
S
STP instruction
R
Reset
S
R
S
WIT instruction
R
CPU
BIU
Clock source for peripheral devices select bit: Bit 2 at address 5F
Watchdog timer frequency select bit
Note: This is the signal generated when the watchdog timer's most significant bit becomes "0."
Fig. 14.2.1 Clock generating circuit block diagram
CLOCK GENERATING CIRCUIT
1
X X
IN OUT
1/2
Q
Q
Ready request
Request of CPU
wait from BIU
Q
: Central Processing Unit
: Bus Interface Unit
: Bit 0 at address 61
7751 Group User's Manual
Clock source for
peripheral devices
select bit
"0"
1/2
1/8 1/4
"1"
1/16
Hold request
BIU
C PU
16
16
14.2 Clock
f /f
2 4
f /f
16 32
Operation clock for
internal peripheral devices
f /f
64 128
f /f
1/8
512 1024
Wf /Wf "1"
32 64
Watchdog
Wf /Wf
512 1024
timer
1/16
"0"
Watchdog timer
frequency
select bit
(Note)
14–3