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APPENDIX
Appendix 9. Q & A
Q
If the processor mode is switched as described below by using the processor mode bits (bits 1
and 0 at address 5E
Single-chip mode → Microprocessor mode
Memory expansion mode → Microprocessor mode
A
If the processor mode is switched as described above by using the processor mode bits, the
mode is switched simultaneously when the cycle to write to the processor mode bits is completed.
Then, the program counter indicates the address next to the address (address XXXX
contains the write instruction for the processor mode bits. Additionally, access to the internal
ROM area is disabled. However, since the instruction queue buffer can prefetch up to three
instructions, the address in the external ROM area and is accessed first after the mode is
switched is one of XXXX
XXXX
+ 3 in the internal ROM area can be executed. To prevent this problem, process the
16
following by software.
Write the write instruction for the processor mode bits and next instructions (at least three
bytes) at the same addresses both in the internal ROM and external ROM areas. (See
below.)
Internal ROM area
:
:
XXXX
LDM. B #00000010B, PMR
16
NOP
NOP
NOP
:
Transfer the write instruction for the processor mode bits to an internal RAM area and make
a branch to there in order to execute the write instruction. After that, make a branch to the
program address in the external ROM area. (Contents of the instruction queue buffer is
initialized by a branch instruction.)
20–78
) during program execution, is there any precaution in software?
16
+ 1 to XXXX
16
16
7751 Group User's Manual
+ 4. The instructions at addresses XXXX
:
:
XXXX
LDM. B #00000010B, PMR
16
NOP
At least
NOP
NOP
three
:
bytes
:
Processor mode
16
External ROM area
) that
16
+ 1 to
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