Renesas 7700 FAMILY User Manual page 465

APPENDIX
Appendix 3. Control registers
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1
UARTi baud rate register (BRGi)
b7
20–14
b0
UART0 transmit/receive mode register (Address 30
UART1 transmit/receive mode register (Address 38
Bit name
Bit
0 Serial I/O mode select bits
1
2
3 Internal/External clock select bit
Stop bit length select bit
4
(Valid in UART mode) (Note)
5 Odd/Even parity select bit
(Valid in UART mode when
parity enable bit is "1") (Note)
6 Parity enable bit
(Valid in UART mode) (Note)
7 Sleep select bit
(Valid in UART mode) (Note)
Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be either "0"
or "1.") Additionally, fix bit 7 to "0."
b0
UART0 baud rate register (Address 31
UART1 baud rate register (Address 39
Bit
7 to 0 Can be set to "00
Assuming that the set value = n, BRGi
divides the count source frequency by n + 1.
7751 Group User's Manual
)
16
)
16
Functions
b2 b1 b0
0 0 0 : Serial I/O disabled
(P8 functions as a programmable
I/O port.)
0 0 1 : Clock synchronous serial I/O
mode
0 1 0 : Not selected
0 1 1 : Not selected
1 0 0 : UART mode
(Transfer data length = 7 bits)
1 0 1 : UART mode
(Transfer data length = 8 bits)
1 1 0 : UART mode
(Transfer data length = 9 bits)
1 1 1 : Not selected
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode cleared (ignored)
1 : Sleep mode selected
)
16
)
16
Functions
" to "FF ."
16 16
At reset
0
0
0
0
0
0
0
0
At reset
RW
WO
Undefined
RW
RW
RW
RW
RW
RW
RW
RW
RW