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13.1.3 Internal processing sequence after reset
Figure 13.1.7 shows the internal processing sequence after reset.
(1) In single-chip and memory expansion modes (CNVss = Vss)
C PU
A
H(CPU)
A
A
M
L(CPU)
DATA
Undefined
(CPU)
E
ALE
Note: The only
(2) In microprocessor mode (CNVss = Vcc)
1
C PU
A
–A
19
16
A
–A
15
0
D
–D
Undefined
15
0
E
ALE
Note: The
CPU
Fig. 13.1.7 Internal processing sequence after reset
00
16
0000
16
IPL, reset vector address
signal is output externaly.
E
0
16
0000
16
IPL, reset vector address
signal is not output
7751 Group User's Manual
00
00
16
16
FFFE
AD
, AD
16
M
L
AD
, AD
Next op-code
M
L
0
16
FFFE
16
AD
, AD
M
L
RESET
13.1 Hardware reset
0
16
AD
, AD
M
L
Next op-code
13–9
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