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APPLICATIONS
17.1 Memory expansion
17.1.2 How to calculate timing
When expanding a memory, use a memory of which standard specifications satisfy the address access
time and the data setup time for write. The following describes how to calculate each timing.
External memory's address access time; t
t
= t
a(AD)
su(P0A/P1A/P2A-P1D/P2D)
Address decode time
Address latch delay time
External memory's data setup time for write; t
t
= t
– t
su(D)
w(EL)
d(E–P2Q/P1Q)
t
: t
d(E–P2Q/P1Q)
d(E–P2Q)
Table 17.1.2 lists the data or the calculation formulas for each parameter. Figure 17.1.1 shows the bus
timing diagram. Figures 17.1.2 and 17.1.4 show the relationship between t
Figures 17.1.3 and 17.1.5 show the relationship between t
Table 17.1.2 Data or calculation formulas for each parameter (unit: ns)
Bus cycle
Low-speed running
Parameter
t
su(P0A/P1A/P2A
3
—P1D/P2D)
f(X
t
w(EL)
2
f(X
t
d(E-P2Q)
t
d(E-P1Q)
17–4
– (address decode time
1
: Time required for the chip select signal to be enabled after decoding address
2
: Delay time required when latching address (Unnecessary in minimum model)
or t
d(E–P1Q)
Low-speed running
3 φ access
2 φ access
5
10
9
10
9
– 65
– 65
f(X
)
)
IN
IN
10
9
9
4
10
– 25
– 25
)
f(X
)
IN
IN
35
35
7751 Group User's Manual
a(AD)
1
+ address latch delay time
su(D)
and f(X
su(D)
Low-speed running
High-speed running
4 φ access
3 φ access
9
7
10
5
10
– 65
f(X
)
f(X
)
IN
IN
3
10
4
10
9
– 25
f(X
)
f(X
)
IN
IN
35
35
2
)
su(P0A/P1A/P2A-P1D/P2D)
).
IN
High-speed running
4 φ access
9
9
7
10
– 75
– 75
f(X
)
IN
9
4
10
9
– 25
– 25
f(X
)
IN
35
and f(X
);
IN
High-speed running
5 φ access
9
10
9
– 75
f(X
)
IN
9
6
10
– 25
f(X
)
IN
35
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