Renesas 7700 FAMILY User Manual page 523

Mitsubishi 16-bit single-chip microcomputer
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APPENDIX
Appendix 9. Q & A
Q
If an interrupt request (b) occurs while executing an interrupt routine (a), is the main routine is not
executed before the INTACK sequence for the next interrupt (b) is executed after the interrupt routine
(a) under execution is completed?
Sequence of
execution
Interrupt routine (a)
Condition
I is cleared to "0" with the RTI instruction.
The interrupt priority level of the interrupt (b) is higher than the main routine IPL.
The interrupt priority detection time is 2 cycles of φ.
A
Sampling for interrupt requests are performed by sampling pulses generated synchronously with the
CPU's op-code fetch cycles.
(1) If the next interrupt request (b) occurs before the sampling pulse (
generated, the microcomputer executes the INTACK sequence for (b) without executing the main
routine (not even one instruction) because sampling is completed while executing the RTI
instruction.
Sampling pulse
(2) If the next interrupt request (b) occurs immediately after generating of the sampling pulse
microcomputer executes one instruction of the main routine before executing the INTACK se-
quence for (b) because the interrupt request is sampled by the next sampling pulse
Sampling pulse
20–72
RTI instruction
Main routine
Interrupt request (b)
RTI instruction
Interrupt routine (a)
RTI instruction
Interrupt routine (a)
7751 Group User's Manual
?
INTACK sequence
for interrupt (b)
INTACK sequence for interrupt (b)
Interrupt request (b)
One instruction executed
Main routine
Interrupt
) for the RTI instruction is
.
INTACK sequence
for interrupt (b)
, the

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