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INTERRUPTS
4.3 Interrupt control
4.3 Interrupt control
The enabling and disabling of maskable interrupts are controlled by the following :
•Interrupt request bit
•Interrupt priority level select bits
•Processor interrupt priority level (IPL)
•Interrupt disable flag (I)
The interrupt disable flag (I) and the processor interrupt priority level (IPL) are assigned to the processor
status register (PS). The interrupt request bit and the interrupt priority level select bits are assigned to the
interrupt control register of each interrupt.
Figure 4.3.1 shows the memory assignment of the interrupt control registers, and Figure 4.3.2 shows their
structure.
Maskable interrupt: An interrupt of which request's acceptance can be disabled by software.
Non-maskable interrupt (including Zero division, BRK instruction, Watchdog timer interrupts):
An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their
interrupt control registers and are independent of the interrupt disable flag (I).
Address
Fig. 4.3.1 Memory assignment of interrupt control registers
4–6
70
A-D conversion interrupt control register
16
71
UART0 transmit interrupt control register
16
72
UART0 receive interrupt control register
16
73
UART1 transmit interrupt control register
16
74
UART1 receive interrupt control register
16
75
Timer A0 interrupt control register
16
76
Timer A1 interrupt control register
16
77
Timer A2 interrupt control register
16
78
Timer A3 interrupt control register
16
79
Timer A4 interrupt control register
16
7A
Timer B0 interrupt control register
16
7B
Timer B1 interrupt control register
16
7C
Timer B2 interrupt control register
16
7D
INT
interrupt control register
16
0
7E
INT
interrupt control register
16
1
7F
INT
interrupt control register
16
2
7751 Group User's Manual
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