Renesas 7700 FAMILY User Manual page 185

SERIAL I/O
7.3 Clock synchronous serial I/O mode
Port P8 direction register (Address 14
b7
0
UART0 receive interrupt control register (Address 72
UART1 receive interrupt control register (Address 74
b7
UART0 transmit buffer register (Address 32
UART1 transmit buffer register (Address 3A
b7
UART0 transmit/receive control register 1 (Address 35
UART1 transmit/receive control register 1 (Address 3D
b7
Fig. 7.3.7 Initial setting example for relevant registers when receiving (2)
7–28
From preceding Figure 7.3.6
)
16
b0
0
R D pin
X 0
R D pin
X 1
b0
Interrupt priority level select bits
When using interrupts, set these bits to level 1–7.
When disabling interrupts, set these bits to level 0.
b0
Set dummy data here.
b0
1 1
Transmit enable bit
1 : Transmission enabled
Receive enable bit
1 : Reception enabled
Note: Set the receive enable bit and the transmit enable bit
Reception starts.
7751 Group User's Manual
)
16
)
16
)
16
)
16
)
16
)
16
to "1" simultaneously.