Page 1 Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.
Page 2 MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER 7700 FAMILY / 7751 SERIES 7751 Group User’s Manual...
Page 3 Preface This manual describes the hardware of the Mitsubishi CMOS 16-bit microcomputers 7751 Group. After reading this manual, the users will be able to understand the functions, so that they can utilize their capabilities fully. For details concerning the software, refer to the 7751 Series Software Manual.
Page 4: Table Of Contents
Table of Contents Table of Contents CHAPTER 1. DESCRIPTION 1.1 Performance overview ......................1-3 1.2 Pin configuration ........................1-4 1.3 Pin description ........................1-5 1.4 Block diagram ........................1-8 CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit ....................... 2-2 2.1.1 Accumulator (Acc) ......................
Page 5 Table of Contents CHAPTER 4. INTERRUPTS 4.1 Overview ..........................4-2 4.2 Interrupt sources ........................4-4 4.3 Interrupt control ........................4-6 4.3.1 Interrupt disable flag (I) ....................4-8 4.3.2 Interrupt request bit ....................... 4-8 4.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL) ..4-8 4.4 Interrupt priority level ......................
Page 6 Table of Contents CHAPTER 6. TIMER B 6.1 Overview ..........................6-2 6.2 Block description ........................6-2 6.2.1 Counter and reload register (timer Bi register) ............6-3 6.2.2 Count start register......................6-4 6.2.3 Timer Bi mode register ....................6-5 6.2.4 Timer Bi interrupt control register ................6-6 6.2.5 Port P6 direction register .....................
Page 7 Table of Contents CHAPTER 8. A-D CONVERTER 8.1 Overview ..........................8-2 8.2 Block description ........................8-3 8.2.1 A-D control register 0 ....................8-4 8.2.2 A-D control register 1 ....................8-6 8.2.3 A-D register i (i = 0 to 7) ..................... 8-7 8.2.4 A-D conversion interrupt control register ..............
Page 8 Table of Contents CHAPTER 11. WAIT MODE 11.1 Clock generating circuit ....................11-2 11.2 Operation description ...................... 11-3 11.2.1 Termination by interrupt request occurrence ............11-4 11.2.2 Termination by hardware reset ................11-4 11.3 Precautions for Wait mode ..................... 11-5 CHAPTER 12.
Page 9 Table of Contents CHAPTER 15. ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings ..................... 15-2 15.2 Recommended operating conditions ................15-3 15.3 Electrical characteristics ....................15-4 15.4 A-D converter characteristics ..................15-5 15.5 Internal peripheral devices ..................... 15-6 15.6 Ready and Hold ....................... 15-13 15.7 Single-chip mode ......................
Page 10 Table of Contents CHAPTER 18. PROM VERSION 18.1 EPROM mode ........................18-3 18.1.1 Pin description ......................18-3 18.1.2 Programming/reading to/from built-in PROM ............18-4 18.1.3 Programming algorithm of built-in PROM ............... 18-7 18.1.4 Electrical characteristics of programming algorithm ..........18-9 18.2 Usage precaution ......................
Page 11 Table of Contents MEMORANDUM viii 7751 Group User’s Manual...
Page 12: Performance Overview
C H A P T E R 1 DESCRIPTION 1.1 Performance overview 1.2 Pin configuration 1.3 Pin description 1.4 Block diagram...
Page 13 DESCRIPTION The 16-bit single-chip microcomputers 7751 Group is suitable for office, business, and industrial equipment controllers that require high-speed processing of large amounts of data. These microcomputers develop with the M37751M6C-XXXFP as the base chip. This manual describes the functions about the M37751M6C-XXXFP unless there is a specific difference and refers to the M37751M6C-XXXFP as “M37751.”...
Page 14 DESCRIPTION 1.1 Performance overview 1.1 Performance overview Table 1.1.1 shows the performance overview of the M37751. Table 1.1.1 M37751 performance overview Functions Parameters Number of basic instructions 100 ns (the minimum instruction at f(X ) = 40 MHz) Instruction execution time 40 MHz (maximum at high-speed running) Operating clock frequency f(X 49152 bytes...
Page 15 DESCRIPTION 1.2 Pin configuration 1.2 Pin configuration Figure 1.2.1 shows the M37751 pin configuration. 80 79 78 77 76 75 74 73 72 71 69 68 67 66 65 /CTS /RTS /TB2 /CLK /TB1 /TB0 /INT /INT /INT /TA4 /TA4 /TA3 /TA3 /TA2...
Page 16 DESCRIPTION 1.3 Pin description 1.3 Pin description Tables 1.3.1 to 1.3.3 list the pin description. Table 1.3.1 Pin description (1) Name Input/Output Functions Power supply Vcc, Vss Supply 5 V ±10 % to Vcc pin and 0 V to Vss pin. CNVss CNVss Input...
Page 17 DESCRIPTION 1.3 Pin description Table 1.3.2 Pin description (2) Functions Name Input/Output –P0 I/O port P0 [Single-chip mode] Port P0 is an 8-bit CMOS I/O port. This port has an I/O direction register and each pin can be programmed for input or output. –A [Memory expansion mode] [Microprocessor mode] Output...
Page 18 DESCRIPTION 1.3 Pin description Table 1.3.3 Pin description (3) Input/Output Name Functions –P4 I/O port P4 [Single-chip mode] Port P4 is an 8-bit I/O port with the same function as can be programmed as the clock φ P0. P4 output pin. _____ Input HOLD,...
Page 19 DESCRIPTION 1.4 Block diagram 1.4 Block diagram Figure 1.4.1 shows the M37751 block diagram. Fig. 1.4.1 M37751 block diagram 1–8 7751 Group User’s Manual...
Page 20: Chapter 2. Central Processing Unit (Cpu)
C H A P T E R 2 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.2 Bus interface unit 2.3 Access space 2.4 Memory assignment 2.5 Processor modes...
Page 21: Accumulator (Acc)
CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1 Central processing unit The CPU (Central Processing Unit) has the ten registers as shown in Figure 2.1.1. Accumulator A (A) Accumulator B (B) Index register X (X) Index register Y (Y) Stack pointer (S) Data bank register (DT) b16 b15...
Page 22 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.1 Accumulator (Acc) Accumulators A and B are available. (1) Accumulator A (A) Accumulator A is the main register of the microcomputer. The transaction of data such as calculation, data transfer, and input/output are performed mainly through accumulator A. It consists of 16 bits, and the low-order 8 bits can also be used separately.
Page 23: Program Counter (Pc)
CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.4 Stack pointer (S) The stack pointer (S) is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used when addressing modes using the stack are executed. The contents of S indicate an address (stack area) for storing registers during subroutine calls and interrupts.
Page 24 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.5 Program counter (PC) The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored.
Page 25: Data Bank Register (Dt)
CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.7 Data bank register (DT) The data bank register is an 8-bit register. In the following addressing modes using the data bank register, the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed. Use the LDT instruction to set a value to this register.
Page 26 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit Direct page area when DPR = “0000 ” Direct page area when DPR = “0123 ” (Note 1) Bank 0 FF10 FFFF Direct page area when DPR = “FF10 ” 10000 (Note 2) 1000F Bank 1 Notes 1 : The number of cycles required to generate an address is 1 cycle smaller when the...
Page 27: Processor Status Register (Ps)
CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.9 Processor status register (PS) The processor status register is an 11-bit register. Figure 2.1.5 shows the structure of the processor status register. Processor status register (PS) Note: Fix bits 11–15 to “0.” Fig.
Page 28 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (6) Bit 5: Data length flag (m) It determines whether to use a data as a 16-bit unit or as an 8-bit unit. A data is treated as a 16- bit unit when this flag is “0,” and as an 8-bit unit when it is “1.” Use the SEM or SEP instruction to set this flag to “1,”...
Page 29: Bus Interface Unit
CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2 Bus interface unit A bus interface unit (BIU) is built-in between the central processing unit (CPU) and memory•I/O devices. BIU’s function and operation are described below. When externally connecting devices, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.” 2.2.1 Overview Transfer operation between the CPU and memory•I/O devices is always performed via the BIU.
Page 30 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit Fig. 2.2.1 Bus and bus interface unit (BIU) 7751 Group User’s Manual 2–11...
Page 31: Functions Of Bus Interface Unit (Biu)
CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2.2 Functions of bus interface unit (BIU) The bus interface unit (BIU) consists of four registers shown in Figure 2.2.2. Table 2.2.1 lists the functions of each register. Program address register Instruction queue buffer Data address register Data buffer Fig.
Page 32 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit The CPU and the bus send or receive data via BIU because each operates based on different clocks (Note). The BIU allows the CPU to operate at high speed without waiting for access to the memory • I/O devices that require a long access time.
Page 33 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (4) Bus control To perform the above operations (1) to (3), the BIU inputs and outputs the control signals, and controls the address bus and the data bus. The cycle in which the BIU controls the bus and accesses the memory•I/O device is called the bus cycle.
Page 34: Operation Of Bus Interface Unit (Biu)
CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2.3 Operation of bus interface unit (BIU) Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU). About signals which are input/output externally when accessing external devices, refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.”...
Page 35 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit Internal address bus (A Address Internal data bus (D Data (Even address) Internal data bus (D Data (Odd address) Address (Odd address) Address (Even address) Internal address bus (A Internal data bus (D Invalid data Data (Even address) Internal data bus (D...
Page 36: Access Space
CENTRAL PROCESSING UNIT (CPU) 2.3 Access space 2.3 Access space Figure 2.3.1 shows the M37751’s access space. By combination of the program counter (PC), which is 16 bits of structure, and the program bank register (PG), a 16-Mbyte space from addresses 0 to FFFFFF can be accessed.
Page 37: Banks
CENTRAL PROCESSING UNIT (CPU) 2.3 Access space 2.3.1 Banks The access space is divided in units of 64 Kbytes. This unit is called “bank.” The high-order 8 bits of address (24 bits) indicate a bank, which is specified by the program bank register (PG) or data bank register (DT).
Page 38: Memory Assignment
CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment 2.4 Memory assignment This section describes the internal area’s memory assignment. For more information about the external area, refer also to section “2.5 Processor modes.” 2.4.1 Memory assignment in internal area SFR (Special Function Register), internal RAM, and internal ROM are assigned in the internal area. Figure 2.4.1 shows the internal area’s memory assignment.
Page 39 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment 000000 SFR area Refer to Figure 2.4.2. 00007F 000080 Internal RAM area 00087F Interrupt vector table FFD6 A-D conversion 004000 FFD8 UART1 transmit FFDA UART1 receive FFDC UART0 transmit FFDE UART0 receive FFE0 Timer B2 FFE2 Timer B1...
Page 40 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment Address Address Count start register Port P0 register One-shot start register Port P1 register Port P0 direction register Up-down register Port P1 direction register Port P2 register Timer A0 register Port P3 register Port P2 direction register Timer A1 register Port P3 direction register...
Page 41: Processor Modes
CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5 Processor modes The M37751 can operate in 3 processor modes: single-chip mode, memory expansion mode, and microprocessor mode. Some pins’ functions, memory assignment, and access space vary according to the processor modes. This section describes the differences between the processor modes.
Page 42: Single-Chip Mode
CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5.1 Single-chip mode Use this mode when not using external devices. In this mode, ports P0 to P8 function as programmable I/O ports (when using an internal peripheral device, they function as its I/O pins). In the single-chip mode, only the internal area (SFR, internal RAM, and internal ROM) can be accessed.
Page 43 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Single-chip mode 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 /CLK /CTS /RTS M37751M6C–XXXFP RESET BYTE 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 Connect this pin to Vss pin in the single-chip mode.
Page 44 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Table 2.5.1 Functions of ports P0 to P4 in each processor mode Processor Single-chip mode Memory expansion/Microprocessor mode modes Pins – A P: Functions as a programmable I/O port. • When external data bus width is 16 bits (BYTE = “L”) P: Functions as a programmable –...
Page 45: Setting Processor Modes
CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5.3 Setting processor modes The voltage supplied to the CNVss pin and the processor mode bits (bits 1 and 0 at address 5E ) set the processor mode. When Vss level is supplied to CNVss pin After a reset, the microcomputer starts operating in the single-chip mode.
Page 46 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Table 2.5.2 Methods for setting processor modes Processor mode CNVss pin level Processor mode bits Single-chip mode Vss (0 V) (Note 1) Memory expansion mode Vss (0 V) (Note 1) Microprocessor mode Vss (0 V) (Note 1) Vcc (5 V) (Note 2) Notes 1: The microcomputer starts operating in the single-chip mode after a reset.
Page 47: [Precautions When Operating In Single-Chip Mode]
CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes [Precautions when operating in single-chip mode] The bus cycle select bits (bits 4 and 5 at address 5F ) is not used in the single-chip mode. However, do not make those bits state of not selected in all cases. Especially in low-speed running, rewrite both bits at the same time to “01 ,”...
Page 48: Chapter 3 Input/Output Pins
C H A P T E R 3 INPUT/OUTPUT PINS 3.1 Programmable I/O ports 3.2 I/O pins of internal peripheral devices...
Page 49 INPUT/OUTPUT PINS 3.1 Programmable I/O ports This chapter describes the programmable I/O ports in the single-chip mode. For P0 to P4, which change their functions according to the processor mode, refer also to the section “2.5 Processor modes” and “Chapter 12. CONNECTION WITH EXTERNAL DEVICES.” 3.1 Programmable I/O ports The 7751 Group has 68 programmable I/O ports, P0 to P8.
Page 50: Direction Register
INPUT/OUTPUT PINS 3.1 Programmable I/O ports 3.1.1 Direction register This register determines the input/output direction of the programmable I/O port. Each bit of this register corresponds one for one to each pin of the microcomputer. Figure 3.1.2 shows the structure of port Pi (i = 0 to 8) direction register. Port Pi direction register (i = 0 to 8) (Addresses 4 , 10...
Page 51: Port Register
INPUT/OUTPUT PINS 3.1 Programmable I/O ports 3.1.2 Port register Data is input/output to/from externals by writing/reading data to/from the port register. The port register consists of a port latch which holds the output data and a circuit which reads the pin state. Each bit of the port register corresponds one for one to each pin of the microcomputer.
Page 52 INPUT/OUTPUT PINS 3.1 Programmable I/O ports Port Pi register (i = 0 to 8) (Addresses 2 , 12 Bit name Functions At reset Port Pi Data is input/output to/from a pin by Undefined reading/writing from/to the corres- Port Pi Undefined ponding bit.
Page 53 INPUT/OUTPUT PINS 3.1 Programmable I/O ports Figures 3.1.4 and 3.1.5 show the port peripheral circuits. [Inside dotted-line not included] Ports P0 to P0 , P1 to P1 , P2 to P2 Direction register to P3 , P4 to P4 [Inside dotted-line included] Data bus Port latch Ports P4...
Page 54 INPUT/OUTPUT PINS 3.1 Programmable I/O ports Ports P8 /CTS /RTS , P8 /CLK “1” “0” /CTS /RTS , P8 /CLK Direction register Output Port latch Data bus E output pin Fig. 3.1.5 Port peripheral circuits (2) 7751 Group User’s Manual 3–7...
Page 55: I/O Pins Of Internal Peripheral Devices
INPUT/OUTPUT PINS 3.2 I/O pins of internal peripheral devices 3.2 I/O pins of internal peripheral devices (P4 , P5–P8) and P5 to P8 also function as the I/O pins of the internal peripheral devices. Table 3.2.1 lists I/O pins for the internal peripheral devices. For their functions, refer to relevant sections of each internal peripheral device.
Page 56: Chapter 4. Interrupts
C H A P T E R 4 INTERRUPTS 4.1 Overview 4.2 Interrupt sources 4.3 Interrupt control 4.4 Interrupt priority level 4.5 Interrupt priority level detection circuit 4.6 Interrupt priority level detection time 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine 4.8 Return from interrupt routine 4.9 Multiple interrupts ____...
Page 57 INTERRUPTS 4.1 Overview The suspension of the current operation in order to perform another operation owing to a certain factor is referred to as “Interrupt.” This chapter describes the interrupts. 4.1 Overview The M37751 has 19 interrupt sources to generate interrupt requests. Figure 4.1.1 shows the interrupt processing sequence.
Page 58 INTERRUPTS 4.1 Overview When an interrupt request is accepted, the contents of the registers listed below immediately preceding the → → . acceptance of the interrupt request are automatically saved to the stack area in order of registers Program bank register (PG) Program counter (PC , PC Processor status register (PS...
Page 59 INTERRUPTS 4.2 Interrupt sources 4.2 Interrupt sources Table 4.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start address of each interrupt routine at the vector addresses listed in this table. Table 4.2.1 Interrupt sources and interrupt vector addresses Interrupt source Interrupt vector address Remarks...
Page 60 INTERRUPTS 4.2 Interrupt sources Table 4.2.2 lists occurrence factors of internal interrupt request, which occur due to internal operation. Table 4.2.2 Occurrence factors of internal interrupt request Interrupt Interrupt request occurrence factors Zero division Occurs when “0” is specified as the divisor for the DIV instruction (Division instruction). interrupt (Refer to “7751 Series Software Manual.”) BRK instruction...
Page 61: Interrupt Disable Flag (I)
INTERRUPTS 4.3 Interrupt control 4.3 Interrupt control The enabling and disabling of maskable interrupts are controlled by the following : •Interrupt request bit •Interrupt priority level select bits •Processor interrupt priority level (IPL) •Interrupt disable flag (I) The interrupt disable flag (I) and the processor interrupt priority level (IPL) are assigned to the processor status register (PS).
Page 62 INTERRUPTS 4.3 Interrupt control A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 70 to 7C Bit name Functions At reset b2 b1 b0 Interrupt priority level select bits 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level...
Page 63: Interrupt Priority Level Select Bits And Processor Interrupt Priority Level (Ipl)
INTERRUPTS 4.3 Interrupt control 4.3.1 Interrupt disable flag (I) All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts are disabled; when the flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1” at reset, clear the flag to “0”...
Page 64 INTERRUPTS 4.3 Interrupt control Table 4.3.1 Setting of interrupt priority level Interrupt priority level select bits Interrupt priority level Priority Level 0 (Interrupt disabled) — Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Table 4.3.2 Interrupt enabled level corresponding to IPL contents Enabled interrupt priority level Enable level 1 and above interrupts.
Page 65: Interrupt Priority Level
INTERRUPTS 4.4 Interrupt priority level 4.4 Interrupt priority level When two or more interrupt requests are detected at the same sampling timing, at which whether an interrupt request exists or not is checked, in the case of the interrupt disable flag (I) = “0” (interrupts enabled);...
Page 66: Interrupt Priority Level Detection Circuit
INTERRUPTS 4.5 Interrupt priority level detection circuit 4.5 Interrupt priority level detection circuit The interrupt priority level detection circuit selects the interrupt having the highest priority level when more than one interrupt request occurs at the same sampling timing. Figure 4.5.1 shows the interrupt priority level detection circuit.
Page 67 INTERRUPTS 4.5 Interrupt priority level detection circuit The following explains the operation of the interrupt priority detection circuit using Figure 4.5.2. The interrupt priority level of a requested interrupt (Y in Figure 4.5.2) is compared with the resultant priority level sent from the preceding comparator (X in Figure 4.5.2); whichever interrupt of the higher priority level is sent to the next comparator (Z in Figure 4.5.2).
Page 68: Interrupt Priority Level Detection Time
INTERRUPTS 4.6 Interrupt priority level detection time 4.6 Interrupt priority level detection time After sampling had started, an interrupt priority level detection time has elapses before an interrupt request is accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the interrupt priority level detection time.
Page 69: Sequence From Acceptance Of Interrupt Request To Execution Of Interrupt Routine
INTERRUPTS 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine The sequence from the acceptance of interrupt request to the execution of the interrupt routine is described below.
Page 70 INTERRUPTS 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine Interrupt request is accepted. Interrupt request occurs. Time Instruction INTACK sequence Instructions in interrupt routine Instruction Interrupt response time @ : Duration for detecting interrupt priority level Time from the occurrence of an interrupt request until the completion of executing an instruction which is being executed at the occurrence.
Page 71: Change In Ipl At Acceptance Of Interrupt Request
INTERRUPTS 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine 4.7.1 Change in IPL at acceptance of interrupt request When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the interrupt priority level of the accepted interrupt. This results in easy control of multiple interrupts. (Refer to section “4.9 Multiple interrupts.”) When at reset or the watchdog timer or the software interrupt is accepted, the value shown in Table 4.7.1 is set in the IPL.
Page 72: Storing Registers
INTERRUPTS 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine 4.7.2 Storing registers The register storing operation performed during INTACK sequence depends on whether the contents of the stack pointer (S) at accepting interrupt request are even or odd. When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the processor status register (PS) are stored as a 16-bit unit simultaneously at each other.
Page 73: Return From Interrupt Routine
INTERRUPTS 4.8 Return from interrupt routine 4.9 Multiple interrupts 4.8 Return from interrupt routine When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank register (PG), program counter (PC), and processor status register (PS) immediately before performing the INTACK sequence, which were saved to the stack area, are automatically restored, and control returns to the routine executed before the acceptance of interrupt request and processing is resumed from it left off.
Page 74 INTERRUPTS 4.9 Multiple interrupts Request Nesting Reset Main routine Time I = 1 IPL = 0 Interrupt 1 I = 0 Interrupt priority level=3 Interrupt 1 I = 1 IPL = 3 Multiple interrupt Interrupt 2 I = 0 Interrupt priority level=5 Interrupt 2 I = 1 IPL = 5...
Page 75: External Interrupts (Int
INTERRUPTS 4.10 External interrupts (INT interrupt) 4.10 External interrupts (INT interrupt) An external interrupt request occurs by input signals to the INT (i = 0 to 2) pin. The occurrence factor of interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit (bits 5 and 4 at addresses 7D to 7F ) shown in Figure 4.10.1.
Page 76 INTERRUPTS 4.10 External interrupts (INT interrupt) to INT interrupt control registers (Addresses 7D to 7F Bit name Functions At reset b2 b1 b0 Interrupt priority level select bits 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3...
Page 77 INTERRUPTS 4.10 External interrupts (INT interrupt) Port P6 direction register (Address 10 Corresponding pin Functions At reset 0 : Input mode 1 : Output mode When using pins as external interrupt input pins,set the corresponding bits to “0.” : Bits 0, 1 and bits 5 to 7 are not used for external interrupts. Fig.
Page 78: Function Of Int
INTERRUPTS 4.10 External interrupts (INT interrupt) 4.10.1 Function of INT interrupt request bit (1) Selecting edge sense mode The interrupt request bit has the same function as that of internal interrupts. That is, when an interrupt request occurs, the interrupt request bit is set to “1.” The bit remains set to “1” until the interrupt request is accepted;...
Page 79 INTERRUPTS 4.10 External interrupts (INT interrupt) When the INT pin’s level changes to an invalid level before an interrupt request is accepted, the interrupt request is not Interrupt request is accepted. retained. Return to main routine. Valid pin level Invalid Main routine Main routine Second interrupt...
Page 80: Switch Of Occurrence Factor Of Int
INTERRUPTS 4.10 External interrupts (INT interrupt) 4.10.2 Switch of occurrence factor of INT interrupt request To switch the occurrence factor of INT interrupt request from the level sense to the edge sense, set the interrupt control register in the sequence shown in Figure 4.10.5 (1). To change the polarity, set the interrupt control register in the sequence shown in Figure 4.10.5 (2).
Page 81 INTERRUPTS 4.11 Precautions when using interrupts 4.11 Precautions when using interrupts ), 2 to 7 cycles of φ To change the interrupt priority level select bits (bits 0 to 2 at addresses 70 to 7F are required after executing an write-instruction until completion of the interrupt priority level’s change. Accordingly, it is necessary to reserve enough time by software when changing the interrupt priority level of which interrupt source is the same within a very short execution time consisting of a few instructions.
Page 82: Overview
C H A P T E R 5 TIMER A 5.1 Overview 5.2 Block description 5.3 Timer mode 5.4 Event counter mode 5.5 One-shot pulse mode 5.6 Pulse width modulation (PWM) mode...
Page 83 TIMER A 5.1 Overview Timer A is used primarily for output to externals. It consists of five counters, timers A0 to A4, each equipped with a 16-bit reload function. Timers A0 to A4 operate independently of one another. 5.1 Overview Timer Ai (i = 0 to 4) has four operating modes listed below.
Page 84 TIMER A 5.2 Block description 5.2 Block description Figure 5.2.1 shows the block diagram of Timer A. Explanation of relevant registers to Timer A is described below. Count source Data bus (odd) select bits Data bus (even) 1024 (Low-order 8 bits) (High-order 8 bits) Timer mode Timer Ai reload register (16)
Page 85: Counter And Reload Register (Timer Ai Register)
TIMER A 5.2 Block description 5.2.1 Counter and reload register (timer Ai register) Each of timer Ai counter and reload register consists of 16 bits. The counter down-counts each time the count source is input. In the event counter mode, it can also function as an up-counter.
Page 86: Count Start Register
TIMER A 5.2 Block description 5.2.2 Count start register This register is used to start and stop counting. Each bit of this register corresponds to each timer. Figure 5.2.2 shows the structure of the count start register. Count start register (Address 40 Bit name Functions At reset...
Page 87: Timer Ai Mode Register
TIMER A 5.2 Block description 5.2.3 Timer Ai mode register Figure 5.2.3 shows the structure of the timer Ai mode register. Operating mode select bits are used to select the operating mode of timer Ai. Bits 2 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode.
Page 88: Timer Ai Interrupt Control Register
TIMER A 5.2 Block description 5.2.4 Timer Ai interrupt control register Figure 5.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer to “Chapter 4. INTERRUPTS.” Timer Ai interrupt control registers (i = 0 to 4) (Addresses 75 to 79 Bit name Functions...
Page 89: Port P5 And Port P6 Direction Registers
TIMER A 5.2 Block description 5.2.5 Port P5 and port P6 direction registers The I/O pins of Timers A0 to A3 are shared with port P5, and the I/O pins of Timer A4 are shared with port P6. When using these pins as Timer Ai’s input pins, set the corresponding bits of the port P5 and port P6 direction registers to “0”...
Page 90: Timer Mode
TIMER A 5.3 Timer mode 5.3 Timer mode In this mode, the timer counts an internally generated count source. (Refer to Table 5.3.1.) Figure 5.3.1 shows the structures of the timer Ai mode register and timer Ai register in the timer mode. Table 5.3.1 Specifications of timer mode Item Specifications...
Page 91 TIMER A 5.3 Timer mode b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 56 to 5A Bit name Functions At reset Operating mode select bits b1 b0 0 0 : Timer mode 0 : No pulse output Pulse output function select bit (TAi...
Page 92: Setting For Timer Mode
TIMER A 5.3 Timer mode 5.3.1 Setting for timer mode Figures 5.3.2 and 5.3.3 show an initial setting example for registers relevant to the timer mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to section “Chapter 4. INTERRUPTS.”...
Page 93 TIMER A 5.3 Timer mode From preceding Figure 5.3.2 . Setting interrupt priority level Timer Ai interrupt control register (i = 0 to 4) (Addresses 75 to 79 Interrupt priority level select bits When using interrupts, set these bits to level 1–7. When disabling interrupts, set these bits to level 0.
Page 94: Count Source
TIMER A 5.3 Timer mode 5.3.2 Count source In the timer mode, the count source select bits (bits 6 and 7 at addresses 56 to 5A ) select the count source. Table 5.3.2 lists the count source frequency. Table 5.3.2 Count source frequency ) = 25 MHz ) = 40 MHz Count source...
Page 95: Operation In Timer Mode
TIMER A 5.3 Timer mode 5.3.3 Operation in timer mode When the count start bit is set to “1,” the counter starts counting of the count source. When the counter underflows, the reload register’s contents are reloaded and counting continues. The timer Ai interrupt request bit is set to “1”...
Page 96: Select Function
TIMER A 5.3 Timer mode 5.3.4 Select function The following describes the selective gate and pulse output functions. (1) Gate function The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 56 to 5A ) to “10 ”...
Page 97 TIMER A 5.3 Timer mode n = Reload register’s contents Starts counting. FFFF Stops counting. 0000 Time Set to “1” by software. “1” Count start bit “0” Count valid pin’s level input signal Invalid level “1” Timer Ai interrupt request bit “0”...
Page 98 TIMER A 5.3 Timer mode (2) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses to 5A ) to “1.” When this function is selected, the TAi pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 and port P6 direction registers.
Page 99 TIMER A 5.3 Timer mode [Precautions when operating in timer mode] By reading the timer Ai register, the counter value can be read out at any timing while counting is in progress. However, if the timer Ai register is read at the reload timing shown in Figure 5.3.7, the value “FFFF ”...
Page 100: Event Counter Mode
TIMER A 5.4 Event counter mode 5.4 Event counter mode In this mode, the timer counts an external signal. (Refer to Tables 5.4.1 and 5.4.2.) Figure 5.4.1 shows the structures of the timer Ai mode register and timer Ai register in the event counter mode. Table 5.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing function) Item...
Page 101 TIMER A 5.4 Event counter mode Table 5.4.2 Specifications of event counter mode (when using two-phase pulse signal processing function with timers A2, A3, and A4) Item Specifications Count source External signal (two-phase pulse) input to the TAj or TAj pin (j = 2 to 4) Count operation...
Page 102 TIMER A 5.4 Event counter mode Timer Ai mode register (i = 0 to 4) (Addresses 56 to 5A Bit name Functions At reset Operating mode select bits b1 b0 0 1 : Event counter mode Pulse output function select bit 0 : No pulse output (TAi functions as a programmable I/O port.)
Page 103: Setting For Event Counter Mode
TIMER A 5.4 Event counter mode 5.4.1 Setting for event counter mode Figures 5.4.2 and 5.4.3 show an initial setting example for registers relevant to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Selecting event counter mode and each function Timer Ai mode register (i = 0 to 4) (Addresses 56...
Page 104 TIMER A 5.4 Event counter mode From preceding Figure 5.4.2 . Setting interrupt priority level Timer Ai interrupt control register (i = 0 to 4) (Addresses 75 to 79 Interrupt priority level select bits When using interrupts, set these bits to level 1-7.
Page 105: Operation In Event Counter Mode
TIMER A 5.4 Event counter mode 5.4.2 Operation in event counter mode When the count start bit is set to “1,” the counter starts counting of the count source. The counter counts the count source’s valid edges. When the counter underflows or overflows, the reload register’s contents are reloaded and counting continues.
Page 106 TIMER A 5.4 Event counter mode (1) Switching between up-count and down-count The up-down register (address 44 ) or the input signal from the TAi pin is used to switch the up- count from and to the down-count. This switching is performed by the up-down bit when the up-down switching factor select bit (bit 4 at addresses 56 to 5A ) is “0,”...
Page 107: Select Functions
TIMER A 5.4 Event counter mode 5.4.3 Select functions The following describes the selective pulse output, and two-phase pulse signal processing functions. (1) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses to 5A ) to “1.”...
Page 108 TIMER A 5.4 Event counter mode (2) Two-phase pulse signal processing function (Timers A2 to A4) For timers A2 to A4, the two-phase pulse signal processing function is selected by setting the two- phase pulse signal processing select bits (bits 5 to 7 at address 44 ) to “1.”...
Page 109 TIMER A 5.4 Event counter mode Quadruple processing The timer up-counts all rising and falling edges to the TA4 and TA4 pins when the phase has the relationship that the TA4 pin’s input signal level goes from “L” to “H” while the TA4 pin’s input signal is “H”...
Page 110 TIMER A 5.4 Event counter mode [Precautions when operating in event counter mode] 1. By reading the timer Ai register, the counter value can be read out at any timing while counting is in progress. However, when the timer Ai register is read at the reload timing shown in Figure 5.4.9, a value “FFFF ”...
Page 111: One-Shot Pulse Mode
TIMER A 5.5 One-shot pulse mode 5.5 One-shot pulse mode In this mode, the timer outputs a pulse which has an arbitrary width once. (Refer to Table 5.5.1.) When a trigger occurs, the timer outputs “H” level from the TAi pin for an arbitrary time.
Page 112 TIMER A 5.5 One-shot pulse mode b4 b3 Timer Ai mode register (i = 0 to 4) (Addresses 56 to 5A Bit name Functions At reset b1 b0 Operating mode select bits 1 0 : One-shot pulse mode Fix this bit to “1” in one-shot pulse mode. b4 b3 Trigger select bits 0 0 : Writing “1”...
Page 113: Setting For One-Shot Pulse Mode
TIMER A 5.5 One-shot pulse mode 5.5.1 Setting for one-shot pulse mode Figures 5.5.2 and 5.5.3 show an initial setting example for registers relevant to the one-shot pulse mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Selecting one-shot pulse mode and each function Timer Ai mode register (i = 0 to 4) (Addresses 56 to 5A...
Page 114 TIMER A 5.5 One-shot pulse mode From preceding Figure 5.5.2. When external trigger When internal trigger is selected is selected Setting port P5 and port P6 direction registers Setting count start bit to “1” Port P5 direction register Count start register (Address 40 (Address D Timer A0 count start bit Timer A1 count start bit...
Page 115: Count Source
TIMER A 5.5 One-shot pulse mode 5.5.2 Count source In the one-shot pulse mode, the count source select bits (bits 6 and 7 at addresses 56 to 5A ) select the count source. Table 5.5.2 lists the count source frequency. Table 5.5.2 Count source frequency ) = 40 MHz ) = 25 MHz...
Page 116: Trigger
TIMER A 5.5 One-shot pulse mode 5.5.3 Trigger The counter is enabled for counting when the count start bit (address 40 ) is set to “1.” The counter starts counting when a trigger is generated after it has been enabled. An internal or an external trigger can be selected as that trigger.
Page 117: Operation In One-Shot Pulse Mode
TIMER A 5.5 One-shot pulse mode 5.5.4 Operation in one-shot pulse mode When the one-shot pulse mode is selected with the operating mode select bits, the TAi pin outputs “L” level. When the count start bit is set to “1,” the counter is enabled for counting. After that, counting starts when a trigger is generated.
Page 118 TIMER A 5.5 One-shot pulse mode n = Reload register’s contents FFFF Stops counting. Starts counting. Stops counting. Starts counting. Reloaded Reloaded 0001 Time Set to “1” by software. “1” Count start bit “0” Trigger during counting “H” input signal “L”...
Page 119 TIMER A 5.5 One-shot pulse mode [Precautions when operating in one-shot pulse mode] 1. If the count start bit is cleared to “0” during counting, the counter stops counting and the TAi pin’s output level becomes “L.” At the same time, the timer Ai interrupt request bit is set to “1.” 2.
Page 120: Pulse Width Modulation (Pwm) Mode
TIMER A 5.6 Pulse width modulation (PWM) mode 5.6 Pulse width modulation (PWM) mode In this mode, the timer continuously outputs pulses which have an arbitrary width. (Refer to Table 5.6.1.) Figure 5.6.1 shows the structures of the timer Ai mode register and timer Ai register in the PWM mode. Table 5.6.1 Specifications of PWM mode Item Specifications...
Page 121 TIMER A 5.6 Pulse width modulation (PWM) mode Timer Ai mode register (i = 0 to 4) (Addresses 56 to 5A Bit name Functions At reset b1 b0 Operating mode select bits 1 1 : PWM mode Fix this bit to “1” in PWM mode. b4 b3 Trigger select bits 0 0 : Writing “1”...
Page 122: Setting For Pwm Mode
TIMER A 5.6 Pulse width modulation (PWM) mode 5.6.1 Setting for PWM mode Figures 5.6.2 and 5.6.3 show an initial setting example for registers relevant to the PWM mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Selecting PWM mode and each function Timer Ai mode register (i = 0 to 4) (Addresses 56 to 5A...
Page 123 TIMER A 5.6 Pulse width modulation (PWM) mode From preceding Figure5.6.2. Setting interrupt priority level Timer Ai interrupt control register (i = 0 to 4) (Addresses 75 to 79 Interrupt priority level select bits When using interrupts, set these bits to level 1 –...
Page 124: Count Source
TIMER A 5.6 Pulse width modulation (PWM) mode 5.6.2 Count source In the PWM mode, the count source select bits (bits 6 and 7 at addresses 56 to 5A ) select the count source. Table 5.6.2 lists the count source frequency. Table 5.6.2 Count source frequency ) = 25 MHz ) = 40 MHz...
Page 125: Operation In Pwm Mode
TIMER A 5.6 Pulse width modulation (PWM) mode 5.6.4 Operation in PWM mode When the PWM mode is selected with the operating mode select bits, the TAi pin outputs “L” level. When a trigger is generated, the counter (pulse width modulator) starts counting and the TAi outputs a PWM pulse (Notes 1 and 2).
Page 126 TIMER A 5.6 Pulse width modulation (PWM) mode 1 / f – 1) Count source “H” pin’s input signal “L” Trigger is not generated by this signal. 1 / f “H” PWM pulse output from TAi “L” “1” Timer Ai interrupt request bit “0”...
Page 127 TIMER A 5.6 Pulse width modulation (PWM) mode 1 / f (m+1) –1) Count source “H” pin’s input signal “L” 1 / f (m+1) “H” 8-bit prescaler’s underflow signal “L” 1 / f (m+1) “H” PWM pulse output from TAi “L”...
Page 128 TIMER A 5.6 Pulse width modulation (PWM) mode Fig. 5.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) 7751 Group User’s Manual 5–47...
Page 129 TIMER A 5.6 Pulse width modulation (PWM) mode [Precautions when operating in PWM mode] 1. If the count start bit is cleared to “0” while outputting PWM pulses, the counter stops counting. When the pin was outputting “H” level at that time, the output level becomes “L” and the timer Ai interrupt request bit is set to “1.”...
Page 130: Overview
C H A P T E R 6 TIMER B 6.1 Overview 6.2 Block description 6.3 Timer mode 6.4 Event counter mode 6.5 Pulse period/pulse width measurement mode...
Page 131 TIMER B 6.1 Overview 6.2 Block description Timer B consists of three counters (Timers B0 to B2) each equipped with a 16-bit reload function. Timers B0 to B2 have identical functions and operate independently with each other. 6.1 Overview Timer Bi (i = 0 to 2) has three operating modes listed below. Timer mode The timer counts an internally generated count source.
Page 132: Counter And Reload Register (Timer Bi Register)
TIMER B 6.2 Block description 6.2.1 Counter and reload register (timer Bi register) Each of timer Bi counter and reload register consists of 16 bits and has the following functions. (1) Functions in timer mode and event counter mode The counter down-counts each time count source is input. The reload register is used to store the initial value of the counter.
Page 133: Count Start Register
TIMER B 6.2 Block description 6.2.2 Count start register This register is used to start and stop counting. Each bit of this register corresponds each timer. Figure 6.2.2 shows the structure of the count start register. b4 b3 Count start register (Address 40 Bit name Functions At reset...
Page 134: Timer Bi Mode Register
TIMER B 6.2 Block description 6.2.3 Timer Bi mode register Figure 6.2.3 shows the structure of the timer Bi mode register. The operating mode select bits are used to select the operating mode of Timer Bi. Bits 2 and 3 and bits 5 to 7 have different functions according to the operating mode.
Page 135: Timer Bi Interrupt Control Register
TIMER B 6.2 Block description 6.2.4 Timer Bi interrupt control register Figure 6.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer to “Chapter 4. INTERRUPTS.” Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A to 7C Bit name Functions...
Page 136: Port P6 Direction Register
TIMER B 6.2 Block description 6.2.5 Port P6 direction register Timer Bi’s input pins are shared with port P6. When using these pins as Timer Bi’s input pins, set the corresponding bits of the port P6 direction register to “0” to set these pins for the input mode. Figure 6.2.5 shows the relationship between port P6 direction register and Timer Bi’s input pins.
Page 137: Timer Mode
TIMER B 6.3 Timer mode 6.3 Timer mode In this mode, the timer counts an internally generated count source. (Refer to Table 6.3.1.) Figure 6.3.1 shows the structures of the timer Bi mode register and timer Bi register in the timer mode. Table 6.3.1 Specifications of timer mode Item Specifications...
Page 138 TIMER B 6.3 Timer mode Timer Bi mode register (i = 0 to 2) (Addresses 5B to 5D Bit name Functions At reset b1 b0 Operating mode select bits 0 0 : Timer mode These bits are ignored in timer mode. –...
Page 139: Setting For Timer Mode
TIMER B 6.3 Timer mode 6.3.1 Setting for timer mode Figure 6.3.2 shows an initial setting example for registers relevant to the timer mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.” Selecting timer mode and count source Timer Bi mode register (i = 0 to 2) (Addresses 5B...
Page 140: Count Source
TIMER B 6.3 Timer mode 6.3.2 Count source In the timer mode, the count source select bits (bits 6 and 7 at addresses 5B to 5D ) select the count source. Table 6.3.2 lists the count source frequency. Table 6.3.2 Count source frequency ) = 25 MHz ) = 40 MHz Count source...
Page 141: Operation In Timer Mode
TIMER B 6.3 Timer mode 6.3.3 Operation in timer mode When the count start bit is set to “1,” the counter starts counting of the count source. When the counter underflows, the reload register’s contents are reloaded and counting continues. The timer Bi interrupt request bit is set to “1”...
Page 142 TIMER B 6.3 Timer mode [Precautions when operating in timer mode] By reading the timer Bi register, the counter value can be read out at any timing while counting is in progress. However, if the timer Bi register is read at the reload timing shown in Figure 6.3.4, the value “FFFF ”...
Page 143: Event Counter Mode
TIMER B 6.4 Event counter mode 6.4 Event counter mode In this mode, the timer counts an external signal. (Refer to Table 6.4.1.) Figure 6.4.1 shows the structures of the timer Bi mode register and the timer Bi register in the event counter mode. Table 6.4.1 Specifications of event counter mode Item Specifications...
Page 144 TIMER B 6.4 Event counter mode Timer Bi mode register (i = 0 to 2) (Addresses 5B to 5D Bit name Functions At reset b1 b0 Operating mode select bits 0 1 : Event counter mode Count polarity select bit b3 b2 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal...
Page 145: Setting For Event Counter Mode
TIMER B 6.4 Event counter mode 6.4.1 Setting for event counter mode Figure 6.4.2 shows an initial setting example for registers relevant to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to section “Chapter 4. INTERRUPTS.”...
Page 146: Operation In Event Counter Mode
TIMER B 6.4 Event counter mode 6.4.2 Operation in event counter mode When the count start bit is set to “1,” the counter starts counting of the count source. The counter counts the count source’s valid edges. When the counter underflows, the reload register’s contents are reloaded and counting continues. The timer Bi interrupt request bit is set to “1”...
Page 147 TIMER B 6.4 Event counter mode [Precautions when operating in event counter mode] By reading the timer Bi register, the counter value can be read out at any timing while counting is in progress. However, if the timer Bi register is read at the reload timing shown in Figure 6.4.4, the value “FFFF ”...
Page 148: Pulse Period/Pulse Width Measurement Mode
TIMER B 6.5 Pulse period/pulse width measurement mode 6.5 Pulse period/pulse width measurement mode In these mode, the timer measures an external signal’s pulse period or pulse width. (Refer to Table 6.5.1.) Figure 6.5.1 shows the structures of the timer Bi mode register and timer Bi register in the pulse period/ pulse width measurement mode.
Page 149 TIMER B 6.5 Pulse period/pulse width measurement mode Timer Bi mode register (i = 0 to 2) (Addresses 5B to 5D Bit name Functions At reset b1 b0 Operating mode select bits 1 0 : Pulse period/Pulse width measurement mode b3 b2 Measurement mode select bits 0 0 : Pulse period measurement...
Page 150: Setting For Pulse Period/Pulse Width Measurement Mode
TIMER B 6.5 Pulse period/pulse width measurement mode 6.5.1 Setting for pulse period/pulse width measurement mode Figure 6.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “Chapter 4. INTERRUPTS.” 7751 Group User’s Manual 6–21...
Page 151 TIMER B 6.5 Pulse period/pulse width measurement mode Selecting pulse period/pulse width measurement mode and each function Timer Bi mode register (i = 0 to 2) (Addresses 5B to 5D Selection of pulse period/pulse width measurement mode Measurement mode select bits b3 b2 0 0 : Pulse period measurement (Interval between falling edges of measured pulse)
Page 152: Count Source
TIMER B 6.5 Pulse period/pulse width measurement mode 6.5.2 Count source In the pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses to 5D ) select the count source. Table 6.5.2 lists the count source frequency. Table 6.5.2 Count source frequency ) = 25 MHz ) = 40 MHz...
Page 153: Operation In Pulse Period/Pulse Width Measurement Mode
TIMER B 6.5 Pulse period/pulse width measurement mode 6.5.3 Operation in pulse period/pulse width measurement mode When the count start bit is set to “1,” the counter starts counting of the count source. The counter value is transferred to the reload register when an valid edge of the measurement pulse is detected.
Page 154 TIMER B 6.5 Pulse period/pulse width measurement mode (2) Timer Bi overflow flag The timer Bi interrupt request occurs when the measurement pulse’s valid edge is input or the counter overflows. The timer Bi overflow flag is used to identify the cause of the interrupt request, that is, whether it is an overflow occurrence or an effective edge input.
Page 155 TIMER B 6.5 Pulse period/pulse width measurement mode Count source “H” Measurement pulse Transferred Transferred “L” Transferred Transferred (measured (undefined (measured (measured value) value) value) value) Reload register counter transfer timing Timing at which counter is cleared to “0000 ” “1”...
Page 156 TIMER B 6.5 Pulse period/pulse width measurement mode [Precautions when operating in pulse period/pulse width measurement mode] 1. The timer Bi interrupt request occurs by the following two causes: Input of measured pulse’s valid edge Counter overflow When the overflow is the cause of the interrupt request occurrence, the timer Bi overflow flag is set to “1.”...
Page 157 TIMER B 6.5 Pulse period/pulse width measurement mode MEMORANDUM 6–28 7751 Group User’s Manual...
Page 158: Overview
C H A P T E R 7 SERIAL I/O 7.1 Overview 7.2 Block description 7.3 Clock synchronous serial I/O mode 7.4 Clock asynchronous serial I/O (UART) mode...
Page 159 SERIAL I/O 7.1 Overview This chapter describes the Serial I/O. The Serial I/O consists of 2 channels: UART0 and UART1. They each have a transfer clock generating timer for the exclusive use of them and can operate independently. UART0 and UART1 have the same functions. 7.1 Overview UARTi (i = 0 and 1) has the following 2 operating modes: Clock synchronous serial I/O mode...
Page 160 SERIAL I/O 7.2 Block description 7.2 Block description Figure 7.2.1 shows the block diagram of Serial I/O. Registers relevant to Serial I/O are described below. Data bus (odd) Data bus (even) Bit converter UARTi receive buffer register UARTi receive register UART 1/16 BRG count source...
Page 161: Uarti Transmit/Receive Mode Register
SERIAL I/O 7.2 Block description 7.2.1 UARTi transmit/receive mode register Figure 7.2.2 shows the structure of UARTi transmit/receive mode register. The serial I/O mode select bits is used to select UARTi’s operating mode. Bits 4 to 6 are described in the section “7.4.2 Transfer data format,”...
Page 162 SERIAL I/O 7.2 Block description (1) Internal/External clock select bit (bit 3) [Clock synchronous serial I/O mode] By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 34 , 3C ) becomes the count source of BRGi (described later).
Page 163: Uarti Transmit/Receive Control Register 1
SERIAL I/O 7.2 Block description 7.2.2 UARTi transmit/receive control register 0 Figure 7.2.3 shows the structure of UARTi transmit/receive control register 0. For bits 0 and 1, refer to “7.2.1 (1) Internal/External clock select bit.” For bit 7, refer to “7.2.2 transfer data format.” UART0 transmit/receive control register 0 (Address 34 UART1 transmit/receive control register 0 (Address 3C Bit name...
Page 164: Uarti Transmit/Receive Control Register 1
SERIAL I/O 7.2 Block description 7.2.3 UARTi transmit/receive control register 1 Figure 7.2.4 shows the structure of UARTi transmit/receive control register 1. For bits 4 to 7, refer to each operation mode’s description. UART0 transmit/receive control register 1 (Address 35 UART1 transmit/receive control register 1 (Address 3D Bit name Functions...
Page 165 SERIAL I/O 7.2 Block description (1) Transmit enable bit (bit 0) By setting this bit to “1,” UARTi enters the transmission enable state. By clearing this bit to “0” during transmission, UARTi enters the transmission disable state after the transmission which is performed at that time is completed.
Page 166: Uarti Transmit Register And Uarti Transmit Buffer Register
SERIAL I/O 7.2 Block description 7.2.4 UARTi transmit register and UARTi transmit buffer register Figure 7.2.5 shows the block diagram of transmit section; Figure 7.2.6 shows the structure of UARTi transmit buffer register. Data bus (odd) Data bus (even) Bit converter UARTi transmit buffer register SP : Stop bit...
Page 167 SERIAL I/O 7.2 Block description The UARTi transmit buffer register is used to set transmit data. Set the transmit data into the low-order byte of this register when operating in the clock synchronous serial I/O mode or when a 7-bit or 8-bit length of transfer data is selected in the UART mode.
Page 168: Uarti Receive Register And Uarti Receive Buffer Register
SERIAL I/O 7.2 Block description 7.2.5 UARTi receive register and UARTi receive buffer register Figure 7.2.7 shows the block diagram of receive section; Figure 7.2.8 shows the structure of UARTi receive buffer register. Data bus (odd) Data bus (even) Bit converter UARTi receive buffer register SP : Stop bit...
Page 169 SERIAL I/O 7.2 Block description The UARTi receive register is used to convert serial data which is input to the RxD pin into parallel data. This register takes in the input signal to the RxD pin synchronously with the transfer clock, one bit at a time.
Page 170: Uarti Baud Rate Register (Brgi)
SERIAL I/O 7.2 Block description 7.2.6 UARTi baud rate register (BRGi) The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer clock. It has a reload register. Assuming that a value set in the BRGi is “n” (n = “00 ”...
Page 171: Uarti Transmit Interrupt Control And Uarti Receive Interrupt Control Registers
SERIAL I/O 7.2 Block description 7.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers When using UARTi, 2 types of interrupts, which are UARTi transmit and UARTi receive interrupts, can be used. Each interrupt has its corresponding interrupt control register. Figure 7.2.12 shows the structure of UARTi transmit interrupt control and UARTi receive interrupt control registers.
Page 172 SERIAL I/O 7.2 Block description (1) Interrupt priority level select bits (bits 0 to 2) These bits select the priority level of the UARTi transmit interrupt or UARTi receive interrupt. When using UARTi transmit/receive interrupt, select priority levels 1 to 7. When the UARTi transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority level is higher than the IPL.
Page 173: Port P8 Direction Register
SERIAL I/O 7.2 Block description 7.2.8 Port P8 direction register I/O pins of UARTi are shared with port P8. When using pins P8 and P8 as serial data input pins (RxD set the corresponding bits of the port P8 direction register to “0” to set these pins for the input mode. When ____ ____ using pins P8 , P8...
Page 174: Clock Synchronous Serial I/O Mode
SERIAL I/O 7.3 Clock synchronous serial I/O mode 7.3 Clock synchronous serial I/O mode Table 7.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 7.3.2 lists the functions of I/O pins in this mode. Table 7.3.1 Performance overview in clock synchronous serial I/O mode Item Functions Transfer data format...
Page 175: Transfer Clock (Synchronizing Clock)
SERIAL I/O 7.3 Clock synchronous serial I/O mode 7.3.1 Transfer clock (synchronizing clock) Data transfer is performed synchronously with the transfer clock. For the transfer clock, the user can select whether to generate the transfer clock internally or to input it from an external. The transfer clock is generated by operation of the transmit control circuit.
Page 176: Transfer Data Format
SERIAL I/O 7.3 Clock synchronous serial I/O mode 7.3.2 Transfer data format LSB first or MSB first can be selected as the transfer data format. Table 7.3.3 lists the relationship between the transfer data format and writing/reading to and from the UARTi transmit/receive buffer register. The transfer format select bit (bit 7 at addresses 34 , 3C ) selects the transfer data format.
Page 177: Method Of Transmission
SERIAL I/O 7.3 Clock synchronous serial I/O mode 7.3.3 Method of transmission Figures 7.3.1 shows an initial setting example for relevant registers when transmitting. Transmission is started when all of the following conditions ( ) are satisfied. When an external clock is selected, satisfy conditions with the following precondition satisfied.
Page 178 SERIAL I/O 7.3 Clock synchronous serial I/O mode UART0 transmit/receive mode register (Address 30 UART1 transmit/receive mode register (Address 38 Clock synchronous serial I/O mode UART0 transmit buffer register (Address 32 UART1 transmit buffer register (Address 3A Internal/External clock select bit 0: Internal clock 1: External clock : It may be either “0”...
Page 179 SERIAL I/O 7.3 Clock synchronous serial I/O mode [When using interrupts] [When not using interrupts] The UARTi transmit interrupt request occurs when the UARTi transmit buffer register becomes empty. Checking state of UARTi transmit buffer register UART0 transmit/receive control register 1 (Address 35 ) UART1 transmit/receive control register 1 (Address 3D ) UARTi transmit interrupt Transmit buffer empty flag...
Page 180 SERIAL I/O 7.3 Clock synchronous serial I/O mode [When using interrupts] [When not using interrupts] The UARTi transmit interrupt request occurs when the transmission starts. Checking start of transmission UART0 transmit interrupt control register (Address 71 UART1 transmit interrupt control register (Address 73 UARTi transmit interrupt Interrupt request bit 0: No interrupt request...
Page 181: Transmit Operation
SERIAL I/O 7.3 Clock synchronous serial I/O mode 7.3.4 Transmit operation When the transmit conditions described in page 7-20 are satisfied, the following operations are automatically performed simultaneously. •The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register. •8 transfer clocks are generated (when an internal clock is selected).
Page 182 SERIAL I/O 7.3 Clock synchronous serial I/O mode Transmit data UARTi transmit buffer register UARTi transmit register Transfer clock Fig. 7.3.4 Transmit operation Transfer clock “1” Transmit enable bit Data is set in UARTi transmit buffer register. “0” “1” Transmit buffer empty flag “0”...
Page 183: Method Of Reception
SERIAL I/O 7.3 Clock synchronous serial I/O mode 7.3.5 Method of reception Figures 7.3.6 and 7.3.7 show initial setting examples for relevant registers when receiving. Reception is started when all of the following conditions ( ) are satisfied. When an external clock is selected, satisfy conditions with the following precondition satisfied.
Page 184 SERIAL I/O 7.3 Clock synchronous serial I/O mode UART0 transmit/receive mode register (Address 30 UART1 transmit/receive mode register (Address 38 Clock synchronous serial I/O mode Internal/External clock select bit 0: Internal clock 1: External clock : It may be either “0” or “1.” UART0 transmit/receive control register 0 (Address 34 UART1 transmit/receive control register 0 (Address 3C BRG count source select bits...
Page 185 SERIAL I/O 7.3 Clock synchronous serial I/O mode From preceding Figure 7.3.6 Port P8 direction register (Address 14 UART0 receive interrupt control register (Address 72 UART1 receive interrupt control register (Address 74 Interrupt priority level select bits When using interrupts, set these bits to level 1–7. When disabling interrupts, set these bits to level 0.
Page 186 SERIAL I/O 7.3 Clock synchronous serial I/O mode [When using interrupts] [When not using interrupts] The UARTi receive interrupt request occurs when reception is completed. Checking completion of reception UART0 transmit/receive control register 1 (Address 35 UART1 transmit/receive control register 1 (Address 3D UARTi receive interrupt Receive complete flag 0: Reception not completed...
Page 187: Receive Operation
SERIAL I/O 7.3 Clock synchronous serial I/O mode 7.3.6 Receive operation When the receive conditions listed on page 7-26 are satisfied, the UARTi enters the receive enable state. The receive operations are described below. The input signal of the RxD pin is taken into the most significant bit of the UARTi receive register synchronously with the rising of the transfer clock.
Page 188 SERIAL I/O 7.3 Clock synchronous serial I/O mode UARTi receive register Transfer clock UARTi receive buffer register Receive data Fig. 7.3.10 Receive operation 7751 Group User’s Manual 7–31...
Page 189 SERIAL I/O 7.3 Clock synchronous serial I/O mode “1” Receive enable bit “0” “1” Transmit enable bit “0” Dummy data is set to UARTi transmit buffer register. “1” Transmit buffer empty flag “0” UARTi transmit register¨← UARTi transmit buffer register “H”...
Page 190: Process On Detecting Overrun Error
SERIAL I/O 7.3 Clock synchronous serial I/O mode 7.3.7 Process on detecting overrun error In the clock synchronous serial I/O mode, an overrun error can be detected. An overrun error occurs when the next data is prepared in the UARTi receive register with the receive complete flag = “1”...
Page 191 SERIAL I/O 7.3 Clock synchronous serial I/O mode [Precautions when operating in clock synchronous serial I/O mode] 1. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, transmit operation (setting for transmission) must be performed. In this case, dummy data is output from the TxD pin.
Page 192: Clock Asynchronous Serial I/O (Uart) Mode
SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode 7.4 Clock asynchronous serial I/O (UART) mode Table 7.4.1 lists the performance overview in the UART mode, and Table 7.4.2 lists the functions of I/O pins in this mode. Table 7.4.1 Performance overview in UART mode Item Functions Transfer data...
Page 193: Transfer Rate (Frequency Of Transfer Clock)
SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode 7.4.1 Transfer rate (frequency of transfer clock) The transfer rate is determined by the BRGi (addresses 31 , 39 When setting “n” into BRGi (n = “00 ” to “FF ”), BRGi divides the count source frequency by n + 1. The divided clock by BRGi is further divided by 16 and the resultant clock becomes the transfer clock.
Page 194 SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode Table 7.4.4 Setting examples of transfer rate (2) ) = 24.576 MHz Transfer Clock source for peripheral devices select bit = “1” Clock source for peripheral devices select bit = “0” BRGi setting Actual time rate (bps)
Page 195: Transfer Data Format
SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode 7.4.2 Transfer data format The transfer data format can be selected from formats shown in Figure 7.4.1. Bits 4 to 6 at addresses 30 and 38 select the transfer data format. (Refer to Figure 7.1.1.) Set the same transfer data format for both transmitter and receiver sides.
Page 196 SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode •Example of 1ST–8DATA–1PAR–1SP Time Transmit/Receive data Next transmit/receive data (When continuously DATA (8 bits) transferring) “H” MSB PAR Fig. 7.4.2 Example of transfer data format Table 7.4.6 Each bit in transmit data Name Functions “L”...
Page 197: Method Of Transmission
SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode 7.4.3 Method of transmission Figure 7.4.3 shows an initial setting example for relevant registers when transmitting. The difference due to selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data length. When selecting a 7- or 8-bit data length, set the transmit data into the low-order byte of the UARTi transmit buffer register.
Page 198 SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode UART0 transmit/receive mode register (Address 30 UART1 transmit/receive mode register (Address 38 UART0 baud rate register (BRG0) (Address 31 UART1 baud rate register (BRG1) (Address 39 b2 b1 b0 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Set to 00...
Page 199 SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode [When using interrupts] [When not using interrupts] The UARTi transmit interrupt request occurs when the UARTi transmit buffer register becomes empty. Checking state of UARTi transmit buffer register UART0 transmit/receive control register 1 (Address 35 UART1 transmit/receive control register 1 (Address 3D UARTi transmit interrupt Transmit buffer empty flag...
Page 200 SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode [When using interrupts] [When not using interrupts] The UARTi transmit interrupt request occurs when the transmission starts. Checking start of transmission UART0 transmit interrupt control register (Address 71 UART1 transmit interrupt control register (Address 73 UARTi transmit interrupt Interrupt request bit No interrupt request...
Page 201: Transmit Operation
SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode 7.4.4 Transmit operation Simultaneously when the transmit conditions listed on page 7-40 are satisfied, the following operations are automatically performed. •The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register. •The transmit buffer empty flag is set to “1.”...
Page 202 SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode Transfer clock “1” Transmit enable bit “0” Data is set in UARTi transmit buffer register. “1” Transmit buffer empty flag “0” UARTi transmit register UARTi transmit buffer register “H” “L” ENDi Stopped because transmit enable bit = “0”...
Page 203: Method Of Reception
SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode 7.4.5 Method of reception Figure 7.4.8 shows an initial setting example for relevant registers when receiving. Reception is started when all of the following conditions ( ) are satisfied: Reception is enabled (receive enable bit = “1”). The start bit is detected.
Page 204 SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode UART0 transmit/receive mode register (Address 30 UART1 transmit/receive mode register (Address 38 UART0 baud rate register (BRG0) (Address 31 UART1 baud rate register (BRG1) (Address 39 b2 b1 b0 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Internal/External clock select bit...
Page 205 SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode [When not using interrupts] [When using interrupts] The UARTi receive interrupt request occurs when reception is completed. Checking completion of reception UART0 transmit/receive control register 1 (Address 35 UART1 transmit/receive control register 1 (Address 3D UARTi receive interrupt Receive complete flag 0 : Reception not completed...
Page 206: Receive Operation
SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode 7.4.6 Receive operation When the receive enable bit is set to “1,” the UARTi enters the reception enabled state and reception starts at detecting ST. The receive operation is described below. The input signal of the RxD pin is taken into the most significant bit of the UARTi receive register synchronously with the transfer clock’s rising.
Page 207 SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode BRGi count source “1” Receive enable bit “0” Stop bit Start bit Sampled “L” Receive data taken in Transfer clock UARTi receive register UARTi receive buffer register Reception started at falling of start bit “1”...
Page 208: Process On Detecting Error
SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode 7.4.7 Process on detecting error Errors listed below can be detected in the UART mode: Overrun error An overrun error occurs when the next data is prepared in the UARTi receive register with the receive completion flag = “1”...
Page 209: Sleep Mode
SERIAL I/O 7.4 Clock asynchronous serial I/O (UART) mode 7.4.8 Sleep mode This mode is used to transfer data between the specified microcomputers, which are connected by using UARTi. The sleep mode is selected by setting the sleep select bit (bit 7 at addresses 30 , 38 ) to “1”...
Page 210: Overview
C H A P T E R 8 A-D CONVERTER 8.1 Overview 8.2 Block description 8.3 A-D conversion method (succesive approximation conversion method) 8.4 Absolute accuracy and differential non-linearity error 8.5 Comparison voltage in 8-bit mode 8.6 One-shot mode 8.7 Repeat mode 8.8 Single sweep mode 8.9 Repeat sweep mode 0 8.10 Repeat sweep mode 1...
Page 211 A-D CONVERTER 8.1 Overview 8.1 Overview The A-D converter has the performance specifications listed in Table 8.1.1. Table 8.1.1 Performance specifications of A-D converter Item Performance specifications A-D conversion method Successive approximation conversion method Resolution Either 8 bits or 10 bits can be selected by software Absolute accuracy 8-bit mode: ±2 LSB 10-bit mode: ±3 LSB...
Page 212: A-D Control Register 0
A-D CONVERTER 8.2 Block description 8.2 Block description Figure 8.2.1 shows the block diagram of the A-D converter. Registers relevant to the A-D converter are described below. A-D conversion frequency selected Register ladder network Successive approximation A-D sweep pin select register 1 register A-D control register 0 A-D register 0...
Page 213: A-D Control Register 1
A-D CONVERTER 8.2 Block description 8.2.1 A-D control register 0 Figure 8.2.2 shows the structure of the A-D control register 0. The A-D operation mode select bits 0 select the operation mode of the A-D converter. The other bits are described below. A-D control register 0 (Address 1E Bit name Functions...
Page 214 A-D CONVERTER 8.2 Block description (2) Trigger select bit (bit 5) This bit is used to select the source of trigger occurrence. (Refer to “(3) A-D conversion start bit.”) (3) A-D conversion start bit (bit 6) When internal trigger is selected Setting this bit to “1”...
Page 215: A-D Control Register 1
A-D CONVERTER 8.2 Block description 8.2.2 A-D control register 1 Figure 8.2.3 shows the structure of the A-D control register 1. The A-D operation mode select bit 1 is used to select the operation mode of the A-D converter. The 8/10- bit mode select bit is used to select the resolution.
Page 216: A-D Register I (I = 0 To 7)
A-D CONVERTER 8.2 Block description 8.2.3 A-D register i (i = 0 to 7) Figure 8.2.4 shows the structure of the A-D register i. When the A-D conversion is completed, the conversion result (contents of the successive approximation register) is stored into this register. Each A-D register i corresponds to an analog input pin (AN ).
Page 217: A-D Conversion Interrupt Control Register
A-D CONVERTER 8.2 Block description 8.2.4 A-D conversion interrupt control register Figure 8.2.5 shows the structure of the A-D conversion interrupt control register. For details about interrupts, refer to “Chapter 4. INTERRUPTS.” A-D conversion interrupt control register (Address 70 Functions Bit name At reset b2 b1 b0...
Page 218: Port P7 Direction Register
A-D CONVERTER 8.2 Block description 8.2.5 Port P7 direction register The A-D converter and port P7 use the same pins in common. When using these pins as the A-D converter’s input pins, set the corresponding bits of the port P7 direction register to “0” to set these ports for the input mode.
Page 219: A-D Conversion Method (Successive Approximation Conversion Method)
A-D CONVERTER 8.3 A-D conversion method (successive approximation conversion method) 8.3 A-D conversion method (successive approximation conversion method) The A-D converter compares the comparison voltage (V ), which is internally generated according to the contents of the successive approximation register, with the analog input voltage (V ), which is input from the analog input pin (AN ).
Page 220 A-D CONVERTER 8.3 A-D conversion method (successive approximation conversion method) Table 8.3.2 Change in successive approximation register and V during A-D conversion in 8-bit mode Change of V Successive approximation register 0 0 0 0 0 0 0 0 0 A-D converter halt 0 0 0 0 0 0 0 0 0 1st comparison...
Page 221 A-D CONVERTER 8.3 A-D conversion method (successive approximation conversion method) A-D conversion result ldeal A-D conversion characteristics 1024 3 1021 1022 1023 1024 1024 1024 1024 1024 Analog input voltage 1024 Fig. 8.3.1 Ideal A-D conversion characteristics in 10-bit mode 7751 Group User’s Manual 8–12...
Page 222: Absolute Accuracy And Differential Non-Linearity Error
A-D CONVERTER 8.4 Absolute accuracy and differential non-linearity error 8.4 Absolute accuracy and differential non-linearity error 8.4.1 Absolute accuracy The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result and the output code of an A-D converter with ideal characteristics. The analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an A-D converter with ideal characteristics.
Page 223: Differential Non-Linearity Error
A-D CONVERTER 8.4 Absolute accuracy and differential non-linearity error 8.4.2 Differential non-linearity error The differential non-linearity error indicates the difference between the 1 LSB step width (the ideal analog input voltage width while the same output code is expected to output) of an A-D converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output).
Page 224: Comparison Voltage In 8-Bit Mode
A-D CONVERTER 8.5 Comparison voltage in 8-bit mode 8.5 Comparison voltage in 8-bit mode In the 8-bit mode, the M37751 treats the high-order 8 bits of the 10-bit successive approximation register as the conversion result. Accordingly, when compared with the 8-bit A-D converter, the A-D conversion of the M37751 is performed by using a comparison reference voltage that is different by 3V /2048 (refer to the underlined portions in the Table 8.5.1).
Page 225: One-Shot Mode
A-D CONVERTER 8.6 One-shot mode 8.6 One-shot mode In the one-shot mode, the operation for the input voltage from the one selected analog input pin is performed once, and an A-D conversion interrupt request occurs when the operation is completed. 8.6.1 Settings for one-shot mode Figure 8.6.1 shows an initial setting example of the one-shot mode.
Page 226 A-D CONVERTER 8.6 One-shot mode A-D control register 0 and A-D control register 1 A-D control register 0 (address 1E A-D control register 1 (address 1F Analog input select bits 8/10-bit mode select bit 0 : 8-bit mode b1 b0 0 0 0 : AN selected 1 : 10-bit mode...
Page 227: One-Shot Mode Operation Description
A-D CONVERTER 8.6 One-shot mode 8.6.2 One-shot mode operation description (1) When an internal trigger is selected The A-D converter starts operation when the A-D conversion start bit is set to “1.” The A-D conversion is completed after 49 cycles of φ in the 8-bit mode, or 59 cycles of φ...
Page 228 A-D CONVERTER 8.6 One-shot mode Trigger occur Conversion result Convert input voltage from A-D register i A-D converter interrupt request occur A-D converter halt Fig. 8.6.2 Conversion operation in one-shot mode 7751 Group User’s Manual 8–19...
Page 229: Repeat Mode
A-D CONVERTER 8.7 Repeat mode 8.7 Repeat mode In the repeat mode, the operation for the input voltage from the one selected analog input pin is performed repeatedly. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E ) remains set to “1”...
Page 230 A-D CONVERTER 8.7 Repeat mode A-D control register 0 and A-D control register 1 A-D control register 0 (address 1E A-D control register 1 (address 1F Analog input select bits 8/10-bit mode select bit b1 b0 0 : 8-bit mode 0 0 0 : AN selected 1 : 10-bit mode...
Page 231: Repeat Mode Operation Description
A-D CONVERTER 8.7 Repeat mode 8.7.2 Repeat mode operation description (1) When an internal trigger is selected The A-D converter starts operation when the A-D conversion start bit is set to “1.” The first A-D conversion is completed after 49 cycles of φ in the 8-bit mode, or 59 cycles of φ...
Page 232: Single Sweep Mode
A-D CONVERTER 8.8 Single sweep mode 8.8 Single sweep mode In the single sweep mode, the operation for the input voltage from multiple selected analog input pins is performed, one at a time. The A-D converter is operated in ascending sequence from the AN pin.
Page 233 A-D CONVERTER 8.8 Single sweep mode A-D control register 0 and A-D control register 1 A-D control register 0 (address 1E A-D control register 1 (address 1F A-D sweep pin select bits Single sweep mode b1 b0 0 0 : AN , AN (2 pins) Trigger select bit...
Page 234: Single Sweep Mode Operation Description
A-D CONVERTER 8.8 Single sweep mode 8.8.2 Single sweep mode operation description (1) When an internal trigger is selected The A-D converter starts conversion for the input voltage from the AN pin starts when the A-D conversion start bit is set to “1.” pin is completed after 49 cycles of φ...
Page 235 A-D CONVERTER 8.8 Single sweep mode Trigger occur Conversion result Convert input voltage from A-D register 0 Conversion result Convert input voltage from A-D register 1 Conversion result Convert input voltage from A-D register i A-D converter interrupt request occur A-D converter halt Fig.
Page 236: Repeat Sweep Mode 0
A-D CONVERTER 8.9 Repeat sweep mode 0 8.9 Repeat sweep mode 0 In the repeat sweep mode 0, the operation for the input voltage from the multiple selected analog input pins is performed repeatedly. The A-D converter is operated in ascending sequence from the AN pin.
Page 237 A-D CONVERTER 8.9 Repeat sweep mode 0 A-D control register 0 and A-D control register 1 A-D control register 0 (address 1E A-D control register 1 (address 1F A-D sweep pin select bits Repeat sweep mode 0 b1 b0 0 0 : AN , AN (2 pins) Trigger select bit...
Page 238: Repeat Sweep Mode 0 Operation Description
A-D CONVERTER 8.9 Repeat sweep mode 0 8.9.2 Repeat sweep mode 0 operation description (1) When an internal trigger is selected The A-D converter starts conversion for the input voltage from the AN pin starts when the A-D conversion start bit is set to “1.” pin is completed after 49 cycles of φ...
Page 239 A-D CONVERTER 8.9 Repeat sweep mode 0 Trigger occur Conversion result Convert input voltage from A-D register 0 Conversion result Convert input voltage from A-D register 1 Conversion result Convert input voltage from A-D register i Fig. 8.9.2 Conversion operation in repeat sweep mode 0 7751 Group User’s Manual 8–30...
Page 240: Settings For Repeat Sweep Mode 1
A-D CONVERTER 8.10 Repeat sweep mode 1 8.10 Repeat sweep mode 1 In the repeat sweep mode 1, the operation for the input voltage from all selected analog input pins is performed repeatedly. In this mode, analog input pins are separated into two groups according to the frequency of use. One is the group for more frequencies of use.
Page 241 A-D CONVERTER 8.10 Repeat sweep mode 1 A-D sweep pin select bit: bits 1, 0 at address 1F = “00 ” (Group of more frequencies of use: AN pin) → → → → → → → → → → → →...
Page 242 A-D CONVERTER 8.10 Repeat sweep mode 1 A-D control register 0 and A-D control register 1 A-D control register 0 (address 1E A-D control register 1 (address 1F A-D sweep pin select bits Repeat sweep mode 1 b1 b0 0 0 : AN (1 pin) Trigger select bit 0 1 : AN...
Page 243: Repeat Sweep Mode 1 Operation Description
A-D CONVERTER 8.10 Repeat sweep mode 1 8.10.2 Repeat sweep mode 1 operation description (1) When an internal trigger is selected The A-D converter starts conversion for the input voltage from the AN pin when the A-D conversion start bit is set to “1.” pin is completed after 49 cycles of φ...
Page 244 A-D CONVERTER [Precautions when using A-D converter] [Precautions when using A-D converter] 1. Write to the following bits and registers before a trigger occurs (while the A-D converter stops operation). • A-D control register 0 (except bit 6) • A-D control register 1 ______ 2.
Page 245 A-D CONVERTER [Precautions when using A-D converter] MEMORANDUM 7751 Group User’s Manual 8–36...
Page 246: Block Description
C H A P T E R 9 WATCHDOG TIMER 9.1 Block description 9.2 Operation description 9.3 Precautions when using watchdog timer...
Page 247 WATCHDOG TIMER 9.1 Block description This chapter describes Watchdog timer. Watchdog timer has the following functions: Detection of a program runaway. Measurement of a certain time when oscillation starts owing to terminating Stop mode. (Refer to “Chapter 10. STOP MODE.”) 9.1 Block description Figure 9.1.1 shows the block diagram of the watchdog timer.
Page 248 WATCHDOG TIMER 9.1 Block description 9.1.1 Watchdog timer Watchdog timer is a 12-bit counter that down-counts the count source which is selected with the watchdog timer frequency select bit (bit 0 at address 61 ). A value “FFF ” is automatically set in Watchdog timer in the cases listed below.
Page 249: Watchdog Timer Frequency Select Register
WATCHDOG TIMER 9.1 Block description 9.1.2 Watchdog timer frequency select register This is used to select the watchdog timer’s count source. Figure 9.1.3 shows the structure of the watchdog timer frequency select register. Watchdog timer frequency select register (Address 61 Bit name Functions At reset...
Page 250: Operation Description
WATCHDOG TIMER 9.2 Operation description 9.2 Operation description The operation of Watchdog timer is described below. 9.2.1 Basic operation Watchdog timer starts down-counting from “FFF .” When the Watchdog timer’s most significant bit becomes “0” (counted 2048 times), the watchdog timer interrupt request occurs.
Page 251 WATCHDOG TIMER 9.2 Operation description (1) Example of program runaway detection Write to the address 60 (watchdog timer register) before the most significant bit of Watchdog timer becomes “0.” In the case that Watchdog timer is used to detect a program runaway, if writing to address 60 is not performed owing to a program runaway, the watchdog timer interrupt request occurs when the most significant bit of Watchdog timer becomes “0.”...
Page 252: Operation In Stop Mode
WATCHDOG TIMER 9.2 Operation description 9.2.2 Operation in Stop mode In Stop mode, Watchdog timer stops operating. Immediately after Stop mode is terminated, Watchdog timer operates as follows. (1) When Stop mode is terminated by a hardware reset Supply of the φ and φ...
Page 253: Precautions When Using Watchdog Timer
WATCHDOG TIMER 9.3 Precautions when using watchdog timer 9.3 Precautions when using watchdog timer 1. When a dummy data is written to address 60 with the 16-bit data length, writing to address 61 simultaneously performed. Accordingly, when the user does not want to change a value of the watchdog timer frequency select bit (bit 0 at address 61 ), write the previous value to the bit simultaneously with writing to address 60...
Page 254: Chapter 10. Stop Mode
C H A P T E R 1 0 STOP MODE 10.1 Clock generating circuit 10.2 Operation description 10.3 Precautions for Stop mode...
Page 255 STOP MODE 10.1 Clock generating circuit This chapter describes Stop mode. Stop mode is used to stop oscillation when there is no need to operate the central processing unit (CPU). The microcomputer enters Stop mode when the STP instruction is executed. Stop mode can be terminated by an interrupt request occurrence or the hardware reset.
Page 256: Operation Description
STOP MODE 10.2 Operation description 10.2 Operation description When the STP instruction is executed, the oscillator stops oscillating. This state is called “Stop mode.” In Stop mode, the contents of the internal RAM can be retained intact when the Vcc, power source voltage, is 2 V or more.
Page 257: Termination By Interrupt Request Occurrence
STOP MODE 10.2 Operation description 10.2.1 Termination by interrupt request occurrence When terminating Stop mode by interrupt request occurrence, instructions are executed after a certain time measured by the watchdog timer has passed. When an interrupt request occurs, the oscillator starts oscillating. Simultaneously, supply of , clock φ φ...
Page 258: Termination By Hardware Reset
STOP MODE 10.2 Operation description Stop mode ..C PU B I U Interrupt request “1” used to terminate Stop mode “0” (Interrupt request bit) 2048 counts “FFF ” Value of watchdog timer “7FF ”...
Page 259: Precautions For Stop Mode
STOP MODE 10.3 Precautions for Stop mode 10.3 Precautions for Stop mode 1. When using the STP instruction with the mask ROM version, select “STP instruction enable” with the STP instruction option on the MASK ROM ORDER CONFIRMATION FORM. The STP instruction is always enabled in the built-in PROM version and the flash memory version. 2.
Page 260: Chapter 11. Wait Mode
C H A P T E R 1 1 WAIT MODE 11.1 Clock generating circuit 11.2 Operation description 11.3 Precautions for Wait mode...
Page 261 WAIT MODE 11.1 Clock generating circuit This chapter describes Wait mode. Wait mode is used to stop when there is no need to operate the central processing unit (CPU). The microcomputer enters Wait mode when the WIT instruction is executed. Wait mode can be terminated by an interrupt request occurrence or the hardware reset.
Page 262 WAIT MODE 11.2 Operation description 11.2 Operation description When the WIT instruction is executed, stop. The oscillator’s oscillation is not stopped. This state is called “Wait mode.” In Wait mode, the microcomputer’s power consumption is reduced though the Vcc, power source voltage, is maintained.
Page 263: Termination By Interrupt Request Occurrence
WAIT MODE 11.2 Operation description 11.2.1 Termination by interrupt request occurrence When an interrupt request occurs, supply of clock starts. The interrupt request which occurs in is accepted. Table 11.2.2 shows the interrupts used to terminate Wait mode. The occurrence of the watchdog timer interrupt request also terminates Wait mode. Table 11.2.2 Interrupts used to terminate Wait mode Interrupt ____...
Page 264: Precautions For Wait Mode
WAIT MODE 11.3 Precautions for Wait mode 11.3 Precautions for Wait mode When executing the WIT instruction after writing to the internal area or an external area, the three NOP instructions must be inserted to complete the write operation before the WIT instruction is executed. Writing instruction NOP instruction insertion WIT instruction...
Page 265 WAIT MODE 11.3 Precautions for Wait mode MEMORANDUM 11–6 7751 Group User’s Manual...
Page 266: Signals Required For Accessing External Devices
C H A P T E R 1 2 CONNECTION WITH EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.2 Bus cycle 12.3 Ready function 12.4 Hold function...
Page 267: Descriptions Of Signals
CONNECTION WITH EXTERNAL DEVICES 12.1 Signals required for accessing external devices This chapter describes functions to connect devices externally. 12.1 Signals required for accessing external devices The functions and operation of the signals which are required for accessing external devices are described below.
Page 268 CONNECTION WITH EXTERNAL DEVICES 12.1 Signals required for accessing external devices External data bus width = 16 bits (BYTE = “L”) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 /CLK /CTS...
Page 269 CONNECTION WITH EXTERNAL DEVICES 12.1 Signals required for accessing external devices Table 12.1.1 Functions of pins P0 to P4 and E pin in memory expansion and microprocessor modes External data bus 8 bits 16 bits width (BYTE = “H”) (BYTE = “L”) to A (P0) —...
Page 270 CONNECTION WITH EXTERNAL DEVICES 12.1 Signals required for accessing external devices (1) External bus (A to A to A to A External areas are specified by the address (A to A ) output. Figure 12.1.2 shows the external area. Pins A to A of the external address bus and pins D to D...
Page 271 CONNECTION WITH EXTERNAL DEVICES 12.1 Signals required for accessing external devices (2) External data bus width switching signal (BYTE pin level) This signal is used to select the external data bus width between 8 bits and 16 bits. When this signal level is “L,”...
Page 272 CONNECTION WITH EXTERNAL DEVICES 12.1 Signals required for accessing external devices (9) Clock φ This signal has the same period as φ . In the memory expansion mode, this signal is output externally by setting the clock φ output select ) to “1.”...
Page 273: Operation Of Bus Interface Unit (Biu)
CONNECTION WITH EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.1.2 Operation of bus interface unit (BIU) Figures 12.1.5 and 12.1.6 show the examples of operating waveforms of the signals input and output to /from externals when accessing external devices. The following explains these waveforms compared with the basic operating waveform (refer to section “2.2.3 Operation of bus interface unit (BIU).”) (1) When fetching instructions into instruction queue buffer When the instruction which is next fetched is located at an even address in the 16-bit external data...
Page 274 CONNECTION WITH EXTERNAL DEVICES 12.1 Signals required for accessing external devices External data bus width = 16 bits (BYTE = “L”) <16-bit data access> (a) Access from even address to A Address to A Address Data(odd) Address Data(even) to A (b) Access from odd address to A Address...
Page 275 CONNECTION WITH EXTERNAL DEVICES 12.1 Signals required for accessing external devices External data bus width = 8 bits (BYTE = “H”) <8/16-bit data access> (e) Access from even address Address Address to A Address Address to A Address Data Address Data to A 8-bit data access...
Page 276: Bus Cycle
CONNECTION WITH EXTERNAL DEVICES 12.2 Bus cycle 12.2 Bus cycle The bus cycle can be selected to make it easy to access the external devices which require a long access time. The bus cycle is selected with the bus cycle select bits (bits 4 and 5 at address 5F The selectable bus cycle depends on the CPU running speed.
Page 277 CONNECTION WITH EXTERNAL DEVICES 12.2 Bus cycle Processor mode register 1 (Address 5F Bit name Functions At reset 1, 0 Fix these bits to “0.” Clock source for peripheral divided by 2 devices select bit (Note) 0 : High-speed running CPU running speed select bit 1 : Low-speed running (Note)
Page 278 CONNECTION WITH EXTERNAL DEVICES 12.2 Bus cycle Table 12.2.2 Bus cycle ) ≤ 40 MHz ] ) ≤ 25 MHz ] High-speed running [ f (X Low-speed running [ f (X Internal area access External area access Internal area access External area access (Note) (Note)
Page 279: Ready Function
CONNECTION WITH EXTERNAL DEVICES 12.3 Ready function 12.3 Ready function Ready function provides the function to facilitate access to external devices that require a long access time. ____ By supplying “L” level to the RDY pin in the memory expansion or microprocessor mode, the microcomputer ____ enters Ready state and retains this state while the RDY pin is at “L”...
Page 280: Operation Description
CONNECTION WITH EXTERNAL DEVICES 12.3 Ready function 12.3.1 Operation description ____ The input level of the RDY pin is judged at the last falling of the clock φ in each bus cycle. Then, when “L” level is detected, the microcomputer enters Ready state. (This is called acceptance of Ready request.) ____ In Ready state, the input level of the RDY pin is judged at every falling of the clock φ...
Page 281 CONNECTION WITH EXTERNAL DEVICES 12.3 Ready function 2 access in low-speed running, 2 access in high-speed running Judgment timing of input level to RDY pin Clock High-speed 2 Low-speed 2 Term unusing bus Term using bus 3 access in low-speed running, 3 access in high-speed running Judgment timing of input level to RDY pin Clock High-speed 3...
Page 282 CONNECTION WITH EXTERNAL DEVICES 12.3 Ready function 4 access in low-speed running, 4 access in high-speed running Judgment timing of input level to RDY pin Clock Term using bus 5 access in high-speed running Judgment timing of input level to RDY pin Clock Term using bus By accepting an Ready request, “L”...
Page 283: Hold Function
CONNECTION WITH EXTERNAL DEVICES 12.4 Hold function 12.4 Hold function When composing the external circuit (DMA) which accesses the bus without using the central processing unit (CPU), the Hold function is used to generate a timing for transferring the right to use the bus from the CPU to the external circuit.
Page 284: Operation Description
CONNECTION WITH EXTERNAL DEVICES 12.4 Hold function 12.4.1 Operation description _____ Judgment timing of the input level of the HOLD pin depends on the state using the bus. While the bus is not in use, the judgment is performed at every falling of φ .
Page 285 CONNECTION WITH EXTERNAL DEVICES 12.4 Hold function _____ Table 12.4.2 Judgment timing of input level of HOLD pin during used bus ) ≤ 40 MHz ] ) ≤ 25 MHz ] High-speed running [ f (X Low-speed running [ f (X Internal area access External area access Internal area access...
Page 286 CONNECTION WITH EXTERNAL DEVICES 12.4 Hold function <When inputting “L” level to pin during term unusing bus> HOLD State when inputting “L” level to HOLD External data bus Data length External data bus width 8, 16 Unused 8, 16 Judgment timing of input level to HOLD pin Clock Floating...
Page 287 CONNECTION WITH EXTERNAL DEVICES 12.4 Hold function <When inputting “L” level to pin during term using bus; when data access is HOLD completed with 1-bus cycle> State when inputting “L” level to HOLD External data bus Data length External data bus width 8, 16 Using (Access from even address)
Page 288 CONNECTION WITH EXTERNAL DEVICES 12.4 Hold function <When inputting “L” level to pin during term using bus; when data access is HOLD completed with continuous 2-bus cycle> State when inputting “L” level to HOLD External data bus Data length External data bus width Using (Access from odd address) Judgment timing of input...
Page 289 CONNECTION WITH EXTERNAL DEVICES 12.4 Hold function MEMORANDUM 7751 Group User’s Manual 12–24...
Page 290: Chapter 13. Reset
C H A P T E R 1 3 RESET 13.1 Hardware reset 13.2 Software reset...
Page 291 RESET 13.1 Hardware reset This chapter describes the method to reset the microcomputer. There are two methods to do that: Hardware reset and Software reset. 13.1 Hardware reset When the power source voltage satisfies the microcomputer’s recommended operating conditions, the ______ microcomputer is reset by supplying “L”...
Page 292: Pin State
RESET 13.1 Hardware reset 13.1.1 Pin state ______ Table 13.1.1 lists the microcomputer’s pin state while the RESET pin is “L” level. ______ Table 13.1.1 Pin state while pin is “L” level RESET pin level Pin (Port) name Pin state Mask ROM version Vss or Vcc P0 to P8...
Page 293: State Of Cpu, Sfr Area, And Internal Ram Area
RESET 13.1 Hardware reset 13.1.2 State of CPU, SFR area, and internal RAM area Figure 13.1.2 shows the state of the CPU registers immediately after reset. Figures 13.1.3 to 13.1.6 show the state of the SFR area and internal RAM areas immediately after reset. 0 : “0”...
Page 294 RESET 13.1 Hardware reset SFR area (0 to 7F : It is possible to read the bit state at reading. The written value becomes valid data. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid data.
Page 295 RESET 13.1 Hardware reset Address State immediately after a reset Register name Access characteristics A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 UART0 transmit/receive mode register UART0 baud rate register UART0 transmit buffer register UART0 transmit/receive control register 0...
Page 296 RESET 13.1 Hardware reset Access characteristics State immediately after a reset Register name Address Count start register One-shot start register Up-down register (Note 1) Timer A0 register (Note 1) (Note 1) Timer A1 register (Note 1) (Note 1) Timer A2 register (Note 1) (Note 1) Timer A3 register...
Page 297 RESET 13.1 Hardware reset Address Register name Access characteristics State immediately after a reset Watchdog timer register (Note 1) (Note 2) Watchdog timer frequency select register (Note 3) A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register...
Page 298: Internal Processing Sequence After Reset
RESET 13.1 Hardware reset 13.1.3 Internal processing sequence after reset Figure 13.1.7 shows the internal processing sequence after reset. (1) In single-chip and memory expansion modes (CNVss = Vss) C PU H(CPU) 0000 FFFE , AD L(CPU) DATA Undefined IPL, reset vector address , AD Next op-code (CPU)
Page 299: Time Supplying "L" Level To Reset Pin
RESET 13.1 Hardware reset ______ 13.1.4 Time supplying “L” level to RESET pin ______ Time supplying “L” level to the RESET pin varies according to the state of the clock oscillation circuit. When the oscillator is stably oscillating or a stable clock is input from the X pin, supply “L”...
Page 300 RESET 13.1 Hardware reset M37751 M51957AL Ω RESET Ω Delay Ω capacity = 0.033 µF. The delay time is about 11 ms when C ≈ [ µs], C 0.34 : [ pF ] Fig. 13.1.9 Example of power-on reset circuit 7751 Group User’s Manual 13–11...
Page 301: Software Reset
RESET 13.2 Software reset 13.2 Software reset When the power source voltage satisfies the microcomputer’s recommended operating conditions, the microcomputer is reset by writing “1” to the software reset bit (bit 3 at address 5E ). This is called a software reset.
Page 302: Oscillation Circuit Example
C H A P T E R 1 4 CLOCK GENERATING CIRCUIT 14.1 Oscillation circuit example 14.2 Clock...
Page 303: Connection Example Using Resonator/Oscillator
CLOCK GENERATING CIRCUIT 14.1 Oscillation circuit example This chapter describes a clock generating circuit which supplies the operating clock of the central processing unit (CPU), bus interface unit (BIU), or internal peripheral devices. The clock generating circuit contains the oscillation circuit. 14.1 Oscillation circuit example To the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock which is externally generated can be input.
Page 304: Clock
CLOCK GENERATING CIRCUIT 14.2 Clock 14.2 Clock Figure 14.2.1 shows the clock generating circuit block diagram. Clock source for peripheral devices Operation clock for select bit internal peripheral devices “0” Interrupt request 1024 “1” “1” 1/16 STP instruction Watchdog Hold request 1024 timer 1/16...
Page 305: Clock Generated In Clock Generating Circuit
CLOCK GENERATING CIRCUIT 14.2 Clock 14.2.1 Clock generated in clock generating circuit (1) φ This is the clock source of φ , φ clock φ to f , Wf and Wf 1024 1024 (2) φ This is the operation clock of CPU. (3) φ...
Page 306: Operation Clock For Internal Peripheral Devices
CLOCK GENERATING CIRCUIT 14.2 Clock 14.2.2 Operation clock for internal peripheral devices The operation clock for the internal peripheral devices uses φ or φ divided by 2 as its clock source. The clock source of the operation clock for internal peripheral devices is selected by the clock source for peripheral devices select bit (bit 2 at address 5F Figure 14.2.2 shows the structure of processor mode register 1 (address 5F When f(X...
Page 307 CLOCK GENERATING CIRCUIT 14.2 Clock MEMORANDUM 14–6 7751 Group User’s Manual...
Page 308: Chapter 15. Electrical Characteristics
C H A P T E R 1 5 ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings 15.2 Recommended operating conditions 15.3 Electrical characteristics 15.4 A-D converter characteristics 15.5 Internal peripheral devices 15.6 Ready and Hold 15.7 Single-chip mode 15.8 Memory expansion mode and microprocessor mode : When 2- φ...
Page 309: Electrical Characteristics
ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings This chapter describes electrical characteristics of the M37751M6C-XXXFP. For the latest data, inquire of addresses described last ( “CONTACT ADDRESSES FOR FURTHER INFORMATION”). 15.1 Absolute maximum ratings Absolute maximum ratings Parameter Symbol Ratings Conditions Unit Power source voltage –0.3 to 7...
Page 310 ELECTRICAL CHARACTERISTICS 15.2 Recommended operating conditions 15.2 Recommended operating conditions = 5 V±10%, Ta = –20 to 85 °C, unless otherwise noted) Recommended operating conditions (V Limits Unit Symbol Parameter Min. Typ. Max. Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage...
Page 311 ELECTRICAL CHARACTERISTICS 15.3 Electrical characteristics 15.3 Electrical characteristics = 0 V, Ta = –20 to 85 °C, f(X Electrical characteristics (V = 5 V, V ) = 40 MHz, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max.
Page 312: A-D Converter Characteristics
ELECTRICAL CHARACTERISTICS 15.4 A-D converter characteristics 15.4 A-D converter characteristics = 0 V, Ta = –20 to 85 °C, unless otherwise noted) A-D CONVERTER CHARACTERISTICS (V = AV = 5 V±10%, V = AV Limits Test conditions Symbol Parameter Unit Typ.
Page 313 ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices 15.5 Internal peripheral devices = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Timing requirements (V = 5 V±10%, V Timer A input (Count input in event counter mode) Limits Symbol Unit Parameter Min.
Page 314 ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices Timer A input (External trigger input in one-shot pulse mode) Limits Data formula (Min.) Symbol Parameter Unit Min. Max. ) ≤ 40 MHz ) ≤ 25 MHz when φ divided by 2 selected as clock input cycle time (Note) c(TA)
Page 315: Internal Peripheral Devices
ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices Internal peripheral devices Count input in event counter mode Gating input in timer mode External trigger input in one-shot pulse mode External trigger input in pulse width modulation mode c(TA) w(TAH) input w(TAL) Up-down input and count input in event counter mode c(UP) w(UPH) input...
Page 316 ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices Timer B input (Count input in event counter mode) Limits Symbol Parameter Unit Min. Max. input cycle time (one edge count) c(TB) input high-level pulse width (one edge count) w(TBH) input low-level pulse width (one edge count) w(TBL) input cycle time (both edges count) c(TB)
Page 317 ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices Timer B input (Pulse width measurement mode) Limits Data formula (Min.) Symbol Parameter Unit Min. Max. ) ≤ 40 MHz ) ≤ 25 MHz when φ divided by 2 selected as clock input cycle time c(TB) source for peripheral devices ) ≤...
Page 318 ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices Serial I/O Limits Parameter Unit Symbol Min. Max. input cycle time c(CK) input high-level pulse width w(CKH) input low-level pulse width w(CKL) output delay time d(C–Q) hold time h(C–Q) input setup time su(D–C) input hold time h(C–D) ____ External interrupt...
Page 319 ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices Internal peripheral devices c(TB) w(TBH) input w(TBL) c(AD) w(ADL) input c(CK) w(CKH) input w(CKL) h(C–Q) output d(C–Q) su(D–C) h(C–D) input w(INL) input w(INH) Test conditions •V = 5 V±10% •Input timing voltage = 1.0 V, V = 4.0 V •Output timing voltage : V = 0.8 V, V...
Page 320: Ready And Hold
ELECTRICAL CHARACTERISTICS 15.6 Ready and Hold 15.6 Ready and Hold = 0 V, Ta = –20 to 85 °C, f(X Timing requirements (V = 5 V±10%, V ) = 40 MHz, unless otherwise noted) Limits Parameter Unit Symbol Min. Max. ____ input setup time su(RDY–...
Page 321 ELECTRICAL CHARACTERISTICS 15.6 Ready and Hold Ready function When 2- access in low-speed running E output RDY input su(RDY– –RDY) When 3- access and 4- access in low-speed running, and 4 - access in high-speed running E output RDY input su(RDY–...
Page 322 ELECTRICAL CHARACTERISTICS 15.6 Ready and Hold Ready function When 3- access in high-speed running E output RDY input su(RDY– –RDY) When 5- access in high-speed running E output RDY input su(RDY– –RDY) Hold function –HOLD) su(HOLD– HOLD input –HLDA) –HLDA) HLDA output Test conditions •V...
Page 323: Single-Chip Mode
ELECTRICAL CHARACTERISTICS 15.7 Single-chip mode 15.7 Single-chip mode = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Timing requirements (V = 5 V±10%, V Limits Symbol Parameter Unit Max. Min. External clock input cycle time External clock input high-level pulse width /2–8 w(H) External clock input low-level pulse width...
Page 324 ELECTRICAL CHARACTERISTICS 15.7 Single-chip mode Single-chip mode W(H) W(L) d(E–P0Q) Port P0 output su(P0D–E) h(E–P0D) Port P0 input d(E–P1Q) Port P1 output su(P1D–E) h(E–P1D) Port P1 input d(E–P2Q) Port P2 output su(P2D–E) h(E–P2D) Port P2 input d(E–P3Q) Port P3 output su(P3D–E) h(E–P3D) Port P3 input...
Page 325: Memory Expansion Mode And Microprocessor Mode : When 2- Φ Access In
ELECTRICAL CHARACTERISTICS 15.8 Memory expansion mode and microprocessor mode : When 2- φ access in low-speed running 15.8 Memory expansion mode and microprocessor mode : When 2- φ access in low-speed running = 0 V, Ta = –20 to 85 °C, f(X Timing requirements (V = 5 V±10%, V ) = 25 MHz, unless otherwise noted)
Page 326 ELECTRICAL CHARACTERISTICS 15.8 Memory expansion mode and microprocessor mode : When 2- φ access in low-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 25 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 327 ELECTRICAL CHARACTERISTICS 15.8 Memory expansion mode and microprocessor mode : When 2- φ access in low-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 25 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 328 ELECTRICAL CHARACTERISTICS 15.8 Memory expansion mode and microprocessor mode : When 2- φ access in low-speed running Memory expansion mode and Microprocessor mode : When 2- access in low-speed running <Write> w(L) w(H) d(E– d(E– w(EL) h(E–P0A) d(P0A–E) Address output Address –A h(E–P1A)
Page 329 ELECTRICAL CHARACTERISTICS 15.8 Memory expansion mode and microprocessor mode : When 2- φ access in low-speed running Memory expansion mode and Microprocessor mode : When 2- access in low-speed running <Read> w(L) w(H) d(E– d(E– w(EL) h(E–P0A) d(P0A–E) Address output Address –A Address output...
Page 330: Memory Expansion Mode And Microprocessor Mode : When 3- Φ Access In
ELECTRICAL CHARACTERISTICS 15.9 Memory expansion mode and microprocessor mode : When 3- φ access in low-speed running 15.9 Memory expansion mode and microprocessor mode : When 3- φ access in low-speed running = 0 V, Ta = –20 to 85 °C, f(X Timing requirements (V = 5 V±10%, V ) = 25 MHz, unless otherwise noted)
Page 331 ELECTRICAL CHARACTERISTICS 15.9 Memory expansion mode and microprocessor mode : When 3- φ access in low-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 25 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 332 ELECTRICAL CHARACTERISTICS 15.9 Memory expansion mode and microprocessor mode : When 3- φ access in low-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 25 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 333 ELECTRICAL CHARACTERISTICS 15.9 Memory expansion mode and microprocessor mode : When 3- φ access in low-speed running Memory expansion mode and Microprocessor mode : When 3- access in low-speed running <Write> w(L) w(H) d(E– d(E– w(EL) d(P0A–E) h(E–P0A) Address output Address –A Address output...
Page 334 ELECTRICAL CHARACTERISTICS 15.9 Memory expansion mode and microprocessor mode : When 3- φ access in low-speed running Memory expansion mode and Microprocessor mode : When 3- access in low-speed running <Read> w(L) w(H) d(E– d(E– w(EL) d(P0A–E) h(E–P0A) Address output Address –A Address output...
Page 335: Memory Expansion Mode And Microprocessor Mode : When 4- Φ Access In
ELECTRICAL CHARACTERISTICS 15.10 Memory expansion mode and microprocessor mode : When 4- φ access in low-speed running 15.10 Memory expansion mode and microprocessor mode : When 4- φ access in low-speed running = 0 V, Ta = –20 to 85 °C, f(X Timing requirements (V = 5 V±10%, V ) = 25 MHz, unless otherwise noted)
Page 336 ELECTRICAL CHARACTERISTICS 15.10 Memory expansion mode and microprocessor mode : When 4- φ access in low-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 25 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 337 ELECTRICAL CHARACTERISTICS 15.10 Memory expansion mode and microprocessor mode : When 4- φ access in low-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 25 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 338 ELECTRICAL CHARACTERISTICS 15.10 Memory expansion mode and microprocessor mode : When 4- φ access in low-speed runninge Memory expansion mode and Microprocessor mode : When 4- access in low-speed running <Write> w(L) w(H) d(E– d(E– w(EL) d(P0A–E) h(E–P0A) Address output Address –A Address output...
Page 339 ELECTRICAL CHARACTERISTICS 15.10 Memory expansion mode and microprocessor mode : When 4- φ access in low-speed runninge Memory expansion mode and Microprocessor mode : When 4- access in low-speed running <Read> w(L) w(H) d(E– d(E– w(EL) d(P0A–E) h(E–P0A) Address output Address –A Address output...
Page 340: High-Speed Running
ELECTRICAL CHARACTERISTICS 15.11 Memory expansion mode and microprocessor mode : When 3- φ access in high-speed running 15.11 Memory expansion mode and microprocessor mode : When 3- φ access in high-speed running = 0 V, Ta = –20 to 85 °C, f(X Timing requirements (V = 5 V±10%, V ) = 40 MHz, unless otherwise noted)
Page 341 ELECTRICAL CHARACTERISTICS 15.11 Memory expansion mode and microprocessor mode : When 3- φ access in high-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 40 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 342 ELECTRICAL CHARACTERISTICS 15.11 Memory expansion mode and microprocessor mode : When 3- φ access in high-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 40 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 343 ELECTRICAL CHARACTERISTICS 15.11 Memory expansion mode and microprocessor mode : When 3- φ access in high-speed running Memory expansion mode and Microprocessor mode : When 3- access in high-speed running <Write> w(L) w(H) d(E– d(E– w(EL) d(P0A–E) h(E–P0A) Address output Address –A Address output...
Page 344 ELECTRICAL CHARACTERISTICS 15.11 Memory expansion mode and microprocessor mode : When 3- φ access in high-speed running Memory expansion mode and Microprocessor mode : When 3- access in high-speed running <Read> w(L) w(H) d(E– d(E– w(EL) d(P0A–E) h(E–P0A) Address output Address –A Address output...
Page 345: High-Speed Running
ELECTRICAL CHARACTERISTICS 15.12 Memory expansion mode and microprocessor mode : When 4- φ access in high-speed running 15.12 Memory expansion mode and microprocessor mode : When 4- φ access in high-speed running = 0 V, Ta = –20 to 85 °C, f(X Timing requirements (V = 5 V±10%, V ) = 40 MHz, unless otherwise noted)
Page 346 ELECTRICAL CHARACTERISTICS 15.12 Memory expansion mode and microprocessor mode : When 4- φ access in high-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 40 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 347 ELECTRICAL CHARACTERISTICS 15.12 Memory expansion mode and microprocessor mode : When 4- φ access in high-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 40 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 348 ELECTRICAL CHARACTERISTICS 15.12 Memory expansion mode and microprocessor mode : When 4- φ access in high-speed running Memory expansion mode and Microprocessor mode : When 4- access in high-speed running <Write> w(L) w(H) d(E– d(E– w(EL) d(P0A–E) h(E–P0A) Address output Address –A Address output...
Page 349 ELECTRICAL CHARACTERISTICS 15.12 Memory expansion mode and microprocessor mode : When 4- φ access in high-speed running Memory expansion mode and Microprocessor mode : When 4- access in high-speed running <Read> w(L) w(H) d(E– d(E– w(EL) d(P0A–E) h(E–P0A) Address output Address –A Address output...
Page 350: Memory Expansion Mode And Microprocessor Mode : When 5- Φ Access In
ELECTRICAL CHARACTERISTICS 15.13 Memory expansion mode and microprocessor mode : When 5- φ access in high-speed running 15.13 Memory expansion mode and microprocessor mode : When 5- φ access in high-speed running = 0 V, Ta = –20 to 85 °C, f(X Timing requirements (V = 5 V±10%, V ) = 40 MHz, unless otherwise noted)
Page 351 ELECTRICAL CHARACTERISTICS 15.13 Memory expansion mode and microprocessor mode : When 5- φ access in high-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 40 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 352 ELECTRICAL CHARACTERISTICS 15.13 Memory expansion mode and microprocessor mode : When 5- φ access in high-speed running = 0 V, Ta = –20 to 85 °C, f(X Switching characteristics (V = 5 V±10%, V ) = 40 MHz, unless otherwise noted) Limits Data formula Symbol...
Page 353 ELECTRICAL CHARACTERISTICS 15.13 Memory expansion mode and microprocessor mode : When 5- φ access in high-speed running Memory expansion mode and Microprocessor mode : When 5- access in high-speed running <Write> w(L) w(H) d(E– d(E– w(EL) d(P0A–E) h(E–P0A) Address output Address –A Address output...
Page 354 ELECTRICAL CHARACTERISTICS 15.13 Memory expansion mode and microprocessor mode : When 5- φ access in high-speed running Memory expansion mode and Microprocessor mode : When 5- access in high-speed running <Read> w(L) w(H) d(E– d(E– w(EL) h(E–P0A) d(P0A–E) Address output Address –A Address output...
Page 355: High-Speed Running (Internal Ram Access)
ELECTRICAL CHARACTERISTICS 15.14 Memory expansion mode and microprocessor mode : When 2- φ access in high-speed running (Internal RAM access) 15.14 Memory expansion mode and microprocessor mode : When 2- φ access in high-speed running (Internal RAM access) Timing requirements (V = 5 V±10%, V = 0 V, Ta = –20 to 85 °C, f(X ) = 40 MHz, unless otherwise noted)
Page 356 ELECTRICAL CHARACTERISTICS 15.14 Memory expansion mode and microprocessor mode : When 2- φ access in high-speed running (Internal RAM access) Memory expansion mode and Microprocessor mode : When 2- access in high-speed running (Internal RAM access) <Write> w(L) w(H) d(E– d(E–...
Page 357 ELECTRICAL CHARACTERISTICS 15.14 Memory expansion mode and microprocessor mode : When 2- φ access in high-speed running (Internal RAM access) Memory expansion mode and Microprocessor mode : When 2- access in high-speed running (Internal RAM access) <Read> w(L) w(H) d(E– d(E–...
Page 358: Testing Circuit For Ports P0 To P8, Φ
ELECTRICAL CHARACTERISTICS 15.15 Testing circuit for ports P0 to P8, φ , and E 15.15 Testing circuit for ports P0 to P8, φ , and E 100pF Fig. 15.15.1 Testing circuit for ports P0 to P8, φ , and E 7751 Group User’s Manual 15–51...
Page 359 ELECTRICAL CHARACTERISTICS 15.15 Testing circuit for ports P0 to P8, φ , and E MEMORANDUM 7751 Group User’s Manual 15–52...
Page 360: Chapter 16. Standard Characteristics
C H A P T E R 1 6 STANDARD CHARACTERISTICS 16.1 Standard characteristics...
Page 361: Programmable I/O Port (Cmos Output) Standard Characteristics
ST ANDARD CHARACTERISTICS 16.1 Standard characteristics 16.1 Standard characteristics Standard characteristics described below are just examples of the M37751M6C-XXXFP’s characteristics and are not guaranteed. For rated values, refer to “Chapter 15. ELECTRICAL CHARACTERISTICS.” 16.1.1 Programmable I/O port (CMOS output) standard characteristics (1) P-channel I –V characteristics...
Page 362: Icc-F
ST ANDARD CHARACTERISTICS 16.1 Standard characteristics 16.1.2 Icc–f(X ) standard characteristics (1) Icc–f(X ) standard characteristics on operating and at reset Measuring conditions (V = 5.0 V, T = 25 °C, f(X ) ; square waveform) On operating in single-chip mode At reset [MHz] (2) Icc–f(X...
Page 363: A-D Converter Standard Characteristics
ST ANDARD CHARACTERISTICS 16.1 Standard characteristics 16.1.3 A-D converter standard characteristics The lower line of the graph indicates the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in output code from 15 to 16 should occurs at 77.5 mV, but the measured value is –1.2 mV.
Page 364 STANDARD CHARACTERISTICS 16.1 Standard characteristics [Measuring conditions] •Vcc = 5.12 V, •V = 5.12 V, •f(X ) = 40 MHz, •Ta = 25 °C 7751 Group User’s Manual 16–5...
Page 365 ST ANDARD CHARACTERISTICS 16.1 Standard characteristics MEMORANDUM 7751 Group User’s Manual 16–6...
Page 366: Chapter 17. Applications
C H A P T E R 1 7 APPLICATIONS 17.1 Memory expansion...
Page 367: Memory Expansion Model
APPLICATIONS 17.1 Memory expansion 17.1 Memory expansion This section shows examples for memory and I/O expansion. Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” for details about the functions and operation of used pins when expanding a memory or I/O. Refer to “Chapter 15. ELECTRICAL CHARACTERISTICS” for timing requirements of the microcomputer. Application shown here are just examples.
Page 368 APPLICATIONS 17.1 Memory expansion Table 17.1.1 Memory expansion model Access area Maximum 64 Kbytes Maximum 16 Mbytes External data bus width M37751 M37751 16+n BYTE –A BYTE 15+n –A 8-bit width; Latch BYTE = “H” –D –D Memory expansion model Memory expansion model Minimum model Medium model A...
Page 369: How To Calculate Timing
APPLICATIONS 17.1 Memory expansion 17.1.2 How to calculate timing When expanding a memory, use a memory of which standard specifications satisfy the address access time and the data setup time for write. The following describes how to calculate each timing. External memory’s address access time;...
Page 370 APPLICATIONS 17.1 Memory expansion External data bus width = 8 bits (BYTE = “H”) w(EL) w(EL) Port P0 Address low-order Address low-order –A Address middle-order Address middle-order Port P1 –A Port P2 External memory Address Address Data output data high-order high-order –A a(AD)
Page 371 APPLICATIONS 17.1 Memory expansion [ns] 1000 4 access in low-speed running 3 access in low-speed running 2 access in low-speed running 323 303 285 268 253 239 247 229 226 215 212 198 185 173 162 152 143 149 135 122 111 101 [MHz] Operation clock frequency f(X...
Page 372 APPLICATIONS 17.1 Memory expansion 350 334 [ns] 5 access in high-speed running 4 access in high-speed running 3 access in high-speed running 189 182 168 161 155 150 150 143 137 130 125 119 114 109 110 103 104 100 [MHz] Operation clock frequency f(X Fig.
Page 373: Points In Memory Expansion
APPLICATIONS 17.1 Memory expansion 17.1.3 Points in memory expansion (1) Reading data Figure 17.1.6 shows the timing at which data is read from an external memory. When reading data, the external data bus is placed in a floating state, and data is read from the external memory.
Page 374 APPLICATIONS 17.1 Memory expansion Table 17.1.3 Values of t and formulas to calculate t (unit : ns) pxz(E–P1Z/P2Z) pzx(E–P1Z/P2Z) Bus cycle Low-speed running Low-speed running High-speed running Low-speed running High-speed running High-speed running 3 φ access 4 φ access 2 φ access 3 φ...
Page 375 APPLICATIONS 17.1 Memory expansion (2) Writing data Figure 17.1.7 shows the timing at which data is written to an external memory. When writing data, the output data is validated after t passes from falling of the E signal. Its d(E-P1Q/P2Q) validated data is output continuously until t passes from rising of the E signal.
Page 376 APPLICATIONS 17.1 Memory expansion (3) Precautions on memory expansion As described in below, if specifications of the external memory do not match those of the M37751, some considerations must be incorporated into circuit design as in the following cases: When using an external memory that requires a long access time, t a(AD) When using an external memory that outputs data within t after falling of the E signal...
Page 377 APPLICATIONS 17.1 Memory expansion M37751 –A Data bus –D Address Address latch decode circuit circuit –A Address bus 1, 2 Use the elements of which propagation delay time is within 12 ns. AC32 AC74 AC04 Ready function is available only for areas accessed by CS ) ≤...
Page 378 APPLICATIONS 17.1 Memory expansion M37751 1 to 3 Use the elements of which sum of –A Data bus propagation delay time is within –D Address –t (RDY– Address decode latch circuit (f(X ) = 25 MHz, 40 ns). circuit –A Address bus AC04 AC32...
Page 379 APPLICATIONS 17.1 Memory expansion M37751 –A Data bus –D 1 to 4 Address Use the elements of which sum of Address decode propagation delay time is within 30.5 ns. latch circuit circuit –A Address bus BC32 BC32 Ready function is available AC04 AC74 only for areas accessed...
Page 380 APPLICATIONS 17.1 Memory expansion M37751 1 to 4 Use the elements of which sum of –A Data bus propagation delay time is within 30.5 ns. –D Address Address decode latch circuit circuit –A Address bus BC32 BC32 Ready function is available only for areas accessed by CS AC04...
Page 381 APPLICATIONS 17.1 Memory expansion When using an external memory that outputs data within t after falling of the E pxz(E-P1Z/P2Z) signal Because the external memory outputs data within t after falling of the E signal, there will pxz(E-P1Z/P2Z) be a possibility of the tail of address colliding with the head of data. In such a case, generate the memory read signal (OE) with delay only the leading edge of the fall of the E.
Page 382 APPLICATIONS 17.1 Memory expansion When using external memory that outputs data for more than t after rising of E pzx(E-P1Z/P2Z) signal Because the external memory outputs data for more than t after rising of the E signal, pzx(E-P1Z/P2Z) there will be a possibility of the tail of data colliding with the head of address. In such a case, examine the method described below: Cut the tail of data output from the external memory by using, for example, a bus buffer.
Page 383 APPLICATIONS 17.1 Memory expansion M37751 –A Address bus AC573 BYTE AC573 F245 – Data bus (odd) F245 – Data bus (even) BC32 AC04 AC32 Circuit condition: 3 access in low-speed running 25 MHz 1: Use the elements of which propagation delay time is within 20 ns. 2, 3 : Use the elements of which sum of output disable time in 2 and propagation delay time in 3 is within 18 ns and the sum of output enable time in 2 and propagation delay time in 3 is 5 ns or more.
Page 384 APPLICATIONS 17.1 Memory expansion <When reading> 135 (min.) 18 (min.) 5 (max.) –A –A BC32 (t BC32 (t OC (F245), RD F245 F245 External memory data output A (F245) <When writing> 135 (min.) 35 (max.) –A –A BC32 (t BC32 (t OC (F245), WO, WE F245 F245...
Page 385 APPLICATIONS 17.1 Memory expansion M37751 –A Address bus AC573 BYTE AC573 ALS245A – Data bus (odd) ALS245A – Data bus (even) This circuit ensures that the rising of the write signal occurs 1/2 clock earlier to extend the write hold time. 1D1Q AC04 AC74...
Page 386 APPLICATIONS 17.1 Memory expansion <When reading> 225 (min.) E, OC (ALS245A) 40.5 (min.) 5 (max.) –A –A AC32 (t AC32 (t ALS245A ALS245A External memory data output A (ALS245A) <When writing> 225 (min.) E, OC (ALS245A) 1Q (AC74) AC04 (t )+AC74 (t 2Q(AC74) AC32...
Page 387 APPLICATIONS 17.1 Memory expansion M37751 –A Address bus AC573 BYTE AC573 F245 – Data bus (odd) F245 – Data bus (even) BC32 AC04 AC32 Circuit condition: 5 access in high-speed running 40 MHz 1: Use the elements of which propagation delay time is within 45 ns. 2, 3 : Use the elements of which sum of output disable time in 2 and propagation delay time in 3 is within 15 ns, and the sum of output enable time in 2 and propagation delay time in 3 is 5 ns or more.
Page 388 APPLICATIONS 17.1 Memory expansion <When reading> 125 (min.) 15 (min.) 5 (max.) –A –A BC32 (t BC32 (t OC (F245), RD F245 F245 External memory data output A (F245) <When writing> 125 (min.) 35 (max.) –A –A BC32 (t OC (F245), WO, WE F245 F245 External memory...
Page 389 APPLICATIONS 17.1 Memory expansion M37751 –A Address bus AC573 BYTE AC573 F245 – Data bus (odd) F245 – Data bus (even) BC32 This circuit ensures that the rising of the write signal occurs 1.5 clock earlier to 1D1Q extend the write hold time. AC04 AC74 AC04...
Page 390 APPLICATIONS 17.1 Memory expansion <When reading> 125 (min.) 15 (min.) 5 (max.) –A –A AC32 (t AC32 (t BC32 (t BC32 (t OC (F245) F245 F245 External memory data output A (F245) <When writing> 125 (min.) 1Q (AC74) AC04 (t )+AC74 (t 2Q (AC74) BC32 (t...
Page 391: Example Of Memory Expansion
APPLICATIONS 17.1 Memory expansion 17.1.4 Example of memory expansion (1) Example of SRAM expansion (minimum model) Figure 17.1.21 shows a memory expansion example (minimum model) using a 32-Kbyte SRAM in the memory expansion mode at the low-speed running. Figure 17.1.22 shows the timing chart for this example.
Page 392 APPLICATIONS 17.1 Memory expansion <When reading> 135 (min.) E, OE 12 (min.) –A 18 (min.) 5 (max.) –D (P0A/P1A/P2A-P1D/P2D) = 135 AC32 (t AC32 (t 15 (max.) (AD) External RAM (Kit guaranteed) data output ≥ 30 (OE) (P2D-E) <When writing> 135 (min.) E, OE –A...
Page 393 APPLICATIONS 17.1 Memory expansion M37751 M5M5256CP-70LL AC32 1, 2: Use the elements of which propagation BYTE delay time is within 15 ns. –A –A –D Memory map –D 0000 SFR area 0080 Internal RAM area Open 0880 External RAM area (M5M5256CP) AC32 4000...
Page 394 APPLICATIONS 17.1 Memory expansion <When reading> 125 (min.) E, OE 40 (min.) 15 (min.) 5 (max.) –A (P0A/P1A/P2A-P1D/P2D) = 150 AC32 (t AC32 (t 15 (max.) (AD) External RAM (Kit guaranteed) data output ≥ 30 (OE) (P2D-E) <When writing> 125 (min.) E, OE –A 35 (max.)
Page 395 APPLICATIONS 17.1 Memory expansion (2) Example of ROM expansion (maximum model) Figure 17.1.25 shows a memory expansion example (maximum model) using a 1-Mbits ROM in the microprocessor mode. Figure 17.1.26 shows the timing chart for this example. Figure 17.1.27 shows a memory expansion example (maximum model) using a 1-Mbits ROM in the microprocessor mode.
Page 396 APPLICATIONS 17.1 Memory expansion <When reading> 135 (min.) E, OE 12 (min.) 5 (max.) 18 (min.) –A 20 (min.) 18 (max.) = 135 (P0A/P1A/P2A-P1D/P2D) +AC573 (t (AD) AC04 (t AC04 (t (OE) 15 (max.) ( Kit guaranteed ) External ROM data output ≥...
Page 397 APPLICATIONS 17.1 Memory expansion 1: Use the elements of which propagation delay time is within 30 ns. 2: Use the elements of which propagation M5M27C102K-12 M37751 delay time is within 35 ns. Address bus –A –A – BYTE AC573 – –A Memory map 0000...
Page 398 APPLICATIONS 17.1 Memory expansion (3) Example of ROM and SRAM expansion (maximum model) Figure 17.1.29 shows a memory expansion example (maximum model) using two 32-Kbytes ROM and two 32-Kbytes SRAM in the microprocessor mode at the low-speed running. Figure 17.1.30 shows the timing chart for this example.
Page 399 APPLICATIONS 17.1 Memory expansion <When reading> 165.4 (min.) 19.6 (min.) –A 5 (max.) –A = 173 su(P0A/P1A/P2A–P1D/P2D) 25.6 (min.) AC573 (t AC04 (t CE, S AC32 (t AC32 (t (OE) 15 (max.) (Kit guaranteed) External memory data output ≥ 30 (P1D/P2D-E) (AD), (CE)
Page 400 APPLICATIONS 17.1 Memory expansion M37751 M5M5256CP-70LL M5M27C256AK-12 Address bus –A BYTE – AC573 – AC04 –A –A –A –A – – – – AC573 – – – – –D –DQ –D –DQ OE W OE W Data bus (odd) Data bus (even) –D AC04 BC32...
Page 401 APPLICATIONS 17.1 Memory expansion <When reading> 104 (min.) 61.7 (min.) –A 5 (max.) –A = 150 (P0A/P1A/P2A-P1D/P2D) 22.2 (min.) AC573 (t AC04 (t CE, S BC32 (t BC32 (t 15 (max.) (Kit guaranteed) (OE) External memory data output ≥ 30 (P1D/P2D-E) (AD), (CE)
Page 402: Example Of I/O Expansion
APPLICATIONS 17.1 Memory expansion 17.1.5 Example of I/O expansion (1) Example of port expansion circuit using M66010FP Figure 17.1.33 shows an example of a port expansion circuit using the M66010FP. Although Figure 17.1.33 is an expansion example in the high-speed running, when using 1.923 MHz or less frequency for Serial I/O transfer clock, the same expansion is possible regardless of the bus cycle.
Page 403 APPLICATIONS 17.1 Memory expansion M37751 M66010FP BYTE Open Expanded I/O port –A – – Circuit condition: •UART0 used in clock synchronous serial I/O mode •Internal clock selected •Frequency of transfer clock = = 1.66 MHz 2 (2 + 1) 40 MHz Fig.
Page 404 APPLICATIONS 17.1 Memory expansion Fig. 17.1.34 Serial transfer timing between M37751 and M66010FP 7751 Group User’s Manual 17–39...
Page 405 APPLICATIONS 17.1 Memory expansion MEMORANDUM 17–40 7751 Group User’s Manual...
Page 406: Chapter 18. Prom Version
C H A P T E R 1 8 PROM VERSION 18.1 EPROM mode 18.2 Usage precaution...
Page 407 PROM VERSION In the PROM version, programming/reading to and from the built-in PROM can be performed by using a general-purpose PROM programmer and a programming adapter. The PROM version has the following two types : One time PROM version Programming to the PROM can be performed once. This version is suitable for a small quantity of and various productions.
Page 408: Pin Description
PROM VERSION 18.1 EPROM mode 18.1 EPROM mode The PROM version can select the normal operating mode which performs the same operation as that of the mask ROM version, or the EPROM mode which enables to program/read to/from the built-in PROM. ______ When “L”...
Page 409 PROM VERSION 18.1 EPROM mode 18.1.2 Programming/reading EPROM mode can perform programming/reading to and from the built-in PROM with the same manner as M5M27C101K. However, there is no device identification code. Accordingly, programming conditions must be set carefully. Perform the programming to addresses 14000 to 1FFFF Table 18.1.3 lists the pin correspondence with M5M27C101K.
Page 410 PROM VERSION 18.1 EPROM mode 80 79 78 77 76 75 74 73 72 71 70 69 68 /CTS /RTS /TB2 /CLK /TB1 /RxD /TB0 /TxD /INT /INT /INT /TA4 /TA4 /TA3 /TA3 /TA2 /TA2 /TA1 /TA1 /TA0 /TA0 /RDY 25 26 27 28 29 30 31 33 34 35 36 37 : Connect an oscillating circuit.
Page 411 PROM VERSION 18.1 EPROM mode Table 18.1.4 Built-in PROM state in EPROM mode Pin name Data I/O Mode Read-out Output Output Floating disable Floating Program 12.5 V Input Program verify 12.5 V Output Program disable 12.5 V Floating : It may be V or V (1) Read When CE and OE pins are set to “L”...
Page 412: Programming Algorithm Of Built-In Prom
PROM VERSION 18.1 EPROM mode 18.1.3 Programming algorithm of built-in PROM Set Vcc = 6 V, V = 12.5 V, and address to 14000 After applying a programming pulse of 0.2 ms, check whether data can be read or not. If the data cannot be read, apply a programming pulse of 0.2 ms again.
Page 413 PROM VERSION 18.1 EPROM mode START ADDR = FIRST LOCATION = 6.0 V = 12.5 V χ = 0 PROGRAM ONE PULSE OF 0.2 ms χ = χ+1 χ = 25 ? FAIL VERIFY FAIL VERIFY DEVICE BYTE BYTE FAILED PASS PASS PROGRAM PULSE...
Page 414: Electrical Characteristics Of Programming Algorithm
PROM VERSION 18.1 EPROM mode 18.1.4 Electrical characteristics of programming algorithm AC electrical characteristics (Ta = 25±5 °C, Vcc = 6±0.25 V, V = 12.5±0.3 V, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. µ s Address setup time µ...
Page 415: Usage Precaution
PROM VERSION 18.2 Usage precaution 18.2 Usage precaution 18.2.1 Precautions on all PROM versions When programming to the built-in PROM, high voltage is required. Accordingly, be careful not to apply excessive voltage to the microcomputer. Furthermore, be especially careful during power-on. Noise gets in easily because the built-in PROM is wired directly from CNV ) pin.
Page 416: Precautions On One Time Prom Version
PROM VERSION 18.2 Usage precaution 18.2.2 Precautions on one time PROM version One time PROM version shipped in a blank (M37751E6CFP), of which built-in PROM is programmed by users, is also provided. For the microcomputer, a programming test and screening are not performed in the assembly process and the following processes.
Page 417 PROM VERSION 18.2 Usage precaution MEMORANDUM 18–12 7751 Group User’s Manual...
Page 418: Chapter 19. Flash Memory Version
C H A P T E R 1 9 FLASH MEMORY VERSION 19.1 Parallel input/output mode 19.2 Serial input/output mode...
Page 419 FLASH MEMORY VERSION In the flash memory version M37751F6CFP, to perform program, read, and erase operations for the built- in flash memory is possible. The M37751F6CFP has the same function as the mask ROM version except for the built–in flash memory (Note). The M37751F6CFP can select the microcomputer mode, which is performed the same operation as the mask ROM version, or the flash memory mode, which enables to access to the built–in flash memory.
Page 420 FLASH MEMORY VERSION 19.1 Parallel input/output mode 19.1 Parallel input/output mode The built-in flash memory can be accessed by using a general purpose ROM programmer in the parallel I/O mode. In this mode, the read–only mode or the read/write mode (software command control mode) can be selected as the built–in flash memory mode with the voltage applied to the V (CNV ) pin.
Page 421: Pin Description
FLASH MEMORY VERSION 19.1 Parallel input/output mode 19.1.1 Pin description Table 19.1.1 lists the pin description in the parallel I/O mode. Table 19.1.1 Pin description in parallel I/O mode Input/Output Functions Name Vcc, Vss Supply 5 V ±10 % to Vcc pin and 0 V to Vss pin. Power supply Input CNVss...
Page 422: Access To Built–In Flash Memory
FLASH MEMORY VERSION 19.1 Parallel input/output mode 19.1.2 Access to built–in flash memory In the parallel I/O mode, the built–in flash memory can be accessed with the same operation as CMOS flash memory M5M28F101. However, because the built–in flash memory has a capacity of 48 Kbytes, use addresses 04000 to 0FFFF for programming and write “FF...
Page 423 FLASH MEMORY VERSION 19.1 Parallel input/output mode 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 /TxD /RxD /CLK /CTS /RTS /R/W /BHE /ALE M37751F6CFP /HLDA RESET BYTE...
Page 424: Read–Only Mode
FLASH MEMORY VERSION 19.1 Parallel input/output mode 19.1.3 Read–only mode When connecting shown in Figure 19.1.3 and V L level is applied to the V pin, the built–in flash memory operates at the read–only mode. In the read–only mode, the built–in flash memory becomes read, output disable, or standby state depending on the control signals.
Page 425 FLASH MEMORY VERSION 19.1 Parallel input/output mode (2) Output disable The microcomputer enters the read disable state. (3) Standby The microcomputer enters the power–saving state and the supply current decreases. 19–8 7751 Group User’s Manual...
Page 426: Read/Write (Software Command Control) Mode
FLASH MEMORY VERSION 19.1 Parallel input/output mode 19.1.4 Read/write (software command control) mode When connecting shown in Figure 19.1.3 and V H level is applied to the V pin, the built–in flash memory operates at the read/write mode. In the read/write mode, the built–in flash memory becomes read, output disable, standby or program state depending on the control signals.
Page 427 FLASH MEMORY VERSION 19.1 Parallel input/output mode (5) Software command In the read/write mode, the built–in flash memory is accessed by input (execution) of the software command. Table 19.1.5 lists the software command. The software command is executed by data input/output in the first and second cycles.
Page 428 FLASH MEMORY VERSION 19.1 Parallel input/output mode Read command Figure 19.1.5 shows the read command execution timing. The command code is latched into the internal command latch at the rising edge of the WE signal by inputting the control signals and the command code “00 ”...
Page 429 FLASH MEMORY VERSION 19.1 Parallel input/output mode Program command Figure 19.1.6 shows the program command and the program verify command execution timing. The command code is latched into the internal command latch at the rising edge of the WE signal by inputting the control signals and the command code “40 ”...
Page 430 FLASH MEMORY VERSION 19.1 Parallel input/output mode Fig. 19.1.6 Program command and program verify command execution timing 7751 Group User’s Manual 19–13...
Page 431 FLASH MEMORY VERSION 19.1 Parallel input/output mode Erase command Figure 19.1.7 shows the erase command and the erase verify command execution timing. The command code is latched into the internal command latch at the rising edge of the WE signal by inputting the control signals and the command code “20 ”...
Page 432 FLASH MEMORY VERSION 19.1 Parallel input/output mode Fig. 19.1.7 Erase command and erase verify command execution timing 7751 Group User’s Manual 19–15...
Page 433 FLASH MEMORY VERSION 19.1 Parallel input/output mode Reset command This command is used to stop executing of program or erase safely after inputting the program or erase command code that is, after the command code is latched into the internal command latch in the first cycle.
Page 434 FLASH MEMORY VERSION 19.1 Parallel input/output mode Device identification command Figure 19.1.9 shows the device identification command execution timing. The command code is latched into the internal command latch at the rising edge of the WE signal by inputting the control signals and the command code “90 ”...
Page 435: Electrical Characteristics
FLASH MEMORY VERSION 19.1 Parallel input/output mode 19.1.5 Electrical characteristics DC electrical characteristics (Ta = 25 °C, V = 5 V±10%, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. Vcc = 5.5 V, CE = V Vcc supply current (at standby) Vcc = 5.5 V, µ...
Page 436 FLASH MEMORY VERSION 19.1 Parallel input/output mode Read/write mode Limits Symbol Unit Parameter Min. Max. Write cycle time Address setup time Address hold time Data setup time Data hold time µ s Write recovery time (before read) µ s Read recovery time (before write) CE setup time CE hold time Write pulse time...
Page 437: Program/Erase Algorithm Flow Chart
FLASH MEMORY VERSION 19.1 Parallel input/output mode 19.1.6 Program/erase algorithm flow chart Program Erase START START = 5V = 5V ADDR = FIRST LOCATION BYTES = 00 X = 0 PROGRAM ALL BYTES = 00 WRITE PROGRAM COMMAND ADDR = FIRST LOCATION WRITE PROGRAM DATA X = 0...
Page 438: Serial Input/Output Mode
FLASH MEMORY VERSION 19.2 Serial input/output mode 19.2 Serial input/output mode In the serial I/O mode, the contents of the built–in flash memory can be reprogrammed with the state mounting the microcomputer on the board. 19.2.1 Pin description Table 19.2.1 lists the pin description in the serial I/O mode. 7751 Group User’s Manual 19–21...
Page 439 FLASH MEMORY VERSION 19.2 Serial input/output mode Table 19.2.1 Pin description in serial I/O mode Name Input/Output Functions Power supply Vcc, Vss Supply 5 V ±10 % to Vcc pin and 0 V to Vss pin. input Input CNVss Supply 12 V ±5 %. External data bus width Input BYTE...
Page 440: Access To Built-In Flash Memory
FLASH MEMORY VERSION 19.2 Serial input/output mode 19.2.2 Access to built–in flash memory Figure 19.2.1 shows the pin connection in the serial I/O mode. When inputting “H” level to the SDA (P4 ), SCLK (P4 ), and OE signal input (P5 ) pins, and after that, applying the V H level to the V...
Page 441 FLASH MEMORY VERSION 19.2 Serial input/output mode 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 /TxD /RxD /CLK /CTS /RTS /R/W /BHE /ALE /HLDA M37751F6CFP RESET BYTE...
Page 442 FLASH MEMORY VERSION 19.2 Serial input/output mode Read command Figure 19.2.2 shows the read command execution timing. The command code “00 ” is input at the first transfer. The low–order 8 bits and the high–order 8 bits are input at the second and third transfer. When setting “L”...
Page 443 FLASH MEMORY VERSION 19.2 Serial input/output mode Program command Figure 19.2.3 shows the program command execution timing. The command code “40 ” is input at the first transfer. The low–order 8 bits and the high–order 8 bits of the address are input at the second and third transfer.
Page 444 FLASH MEMORY VERSION 19.2 Serial input/output mode Program verify command Figure 19.2.4 shows the program verify command execution timing. This command is executed to verify data of address where the program command has been executed after executing the program command. The command code “C0 ”...
Page 445 FLASH MEMORY VERSION 19.2 Serial input/output mode Auto erase command Figure 19.2.5 shows the auto erase command execution timing. The command code “30 ” is input at the first transfer. The command code “30 ” is input again at the second transfer. Erasing is started at the last rising edge of the second transfer serial clock and the BUSY signal becomes “H”...
Page 446 FLASH MEMORY VERSION 19.2 Serial input/output mode Error check command Figure 19.2.6 shows the error check command execution timing. The command code “80 ” is input at the first transfer. When inputting the serial clock, the error information is output externally. When an error occurs, the serial communication circuit sets the corresponding error flag to “1”...
Page 447 FLASH MEMORY VERSION 19.2 Serial input/output mode Command error flag (E0) When inputting the code other than the five command codes shown in Table 19.2.2, this flag becomes “1.” Address error flag (E1) When inputting the addresses other than addresses 4000 to FFFF , this flag becomes “1.”...
Page 448: Electrical Characteristics
FLASH MEMORY VERSION 19.2 Serial input/output mode 19.2.3 Electrical characteristics DC electrical characteristics (Ta = 25 °C, V = 5 V±10%, V = 12 V±5%, unless otherwise noted) Limits Symbol Test conditions Parameter Unit Min. Typ. Max. Vcc = 5.5 V, t = 320 ns, Vcc supply current (at read) = 0 mA...
Page 449 FLASH MEMORY VERSION 19.2 Serial input/output mode Timing C(CK) (CK) W(CKL) W(CKH) (CK) SCLK (C-Q) (C-Q) (C-E) SDA output (D-C) (C-D) SDA input Test conditions •Output timing voltage : V = 0.8 V, V = 2.0 V •Input timing voltage : V = 0.2 V = 0.8 V 19–32...
Page 450: Program Algorithm Flow Chart
FLASH MEMORY VERSION 19.2 Serial input/output mode 19.2.4 Program algorithm flow chart START = 5 V SDA = SCLK = OE = “H” ADDR = FIRST LOCATION X = 0 WRITE PROGRAM COMMAND WRITE PROGRAM DATA DURATION = 10 µs X = X + 1 WRITE PROGRAM-VERIFY COMMAND...
Page 451 FLASH MEMORY VERSION 19.2 Serial input/output mode MEMORANDUM 19–34 7751 Group User’s Manual...
Page 452: Appendix
A P P E N D I X Appendix 1. Memory assignment Appendix 2. Memory assignment in SFR area Appendix 3. Control registers Appendix 4. Package outlines Appendix 5. Example for processing unused pins Appendix 6. Hexadecimal instruction code table Appendix 7.
Page 453 APPENDIX Appendix 1. Memory assignment Appendix 1. Memory assignment 1. During single-chip mode 000000 SFR area 000080 Internal RAM 2048 bytes 00087F Not used 004000 Internal ROM 48 Kbytes 00FFFF M37751M6C-XXXFP M37751E6C-XXXFP Type name M37751E6CFS M37751F6CFP Fig. 1. Memory assignment during single-chip mode 7751 Group User’s Manual 20–2...
Page 454 APPENDIX Appendix 1. Memory assignment 2. During memory expansion mode SFR area 000000 SFR area 000002 000080 External area 000009 Internal RAM area 2048 bytes 00087F External area Bank 004000 Internal ROM area 48 Kbytes 00FFFF 010000 Bank 01FFFF External area FF0000 Bank FFFFFF...
Page 455 APPENDIX Appendix 1. Memory assignment 3. During microprocessor mode SFR area 000000 SFR area 000002 000080 External area 000009 Internal RAM area 2048 bytes 00087F Bank Note: Interrupt vector table is assigned to addresses FFD6 to FFFF Set a ROM to this area. External area 00FFFF 010000...
Page 456 APPENDIX Appendix 2. Memory assignment in SFR area Appendix 2. Memory assignment in SFR area Access characteristics : It is possible to read the bit state at reading. The written value becomes valid data. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid data.
Page 457 APPENDIX Appendix 2. Memory assignment in SFR area Access characteristics : It is possible to read the bit state at reading. The written value becomes valid data. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid data.
Page 458 APPENDIX Appendix 2. Memory assignment in SFR area Access characteristics : It is possible to read the bit state at reading. The written value becomes valid data. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid data.
Page 459 APPENDIX Appendix 2. Memory assignment in SFR area Access characteristics : It is possible to read the bit state at reading. The written value becomes valid data. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid data.
Page 460 APPENDIX Appendix 3. Control registers Appendix 3. Control registers The register structure of each control register assignment in the SFR area are shown on the following pages. The view of the register structure is described below. XXX register (Address XX Bit name Functions At reset...
Page 461 APPENDIX Appendix 3. Control registers Port Pi register Port Pi register (i = 0 to 8) (Addresses 2 , 12 Bit name Functions At reset Port Pi Data is input/output to/from a pin by Undefined reading/writing from/to the corres- Port Pi Undefined ponding bit.
Page 462 APPENDIX Appendix 3. Control registers A-D control register 0 A-D control register 0 (Address 1E Bit name Functions At reset b2 b1 b0 Analog input select bits 0 0 0 : AN selected Undefined (Valid in one-shot and repeat 0 0 1 : AN selected modes) (Note 1) 0 1 0 : AN...
Page 463 APPENDIX Appendix 3. Control registers A-D control register 1 A-D control register 1 (Address 1F Bit name Functions At reset Single sweep mode/Repeat sweep A-D sweep pin select bits mode 0 (Valid in single sweep, repeat sweep b1 b0 mode 0 and repeat sweep mode 1) 0 0 : AN , AN (2 pins)
Page 464 APPENDIX Appendix 3. Control registers A-D register i A-D register 0 (Addresses 21 , 20 8-bit mode A-D register 1 (Addresses 23 , 22 A-D register 2 (Addresses 25 , 24 (b15) (b8) A-D register 3 (Addresses 27 , 26 A-D register 4 (Addresses 29 , 28 A-D register 5 (Addresses 2B...
Page 465 APPENDIX Appendix 3. Control registers UARTi transmit/receive mode register UART0 transmit/receive mode register (Address 30 UART1 transmit/receive mode register (Address 38 Bit name Functions At reset b2 b1 b0 Serial I/O mode select bits 0 0 0 : Serial I/O disabled (P8 functions as a programmable I/O port.) 0 0 1 : Clock synchronous serial I/O...
Page 466 APPENDIX Appendix 3. Control registers UARTi transmit buffer register (b15) (b8) UART0 transmit buffer register (Addresses 33 , 32 UART1 transmit buffer register (Addresses 3B , 3A Functions At reset Transmit data is set. 8 to 0 Undefined – 15 to 9 Nothing is assigned.
Page 467 APPENDIX Appendix 3. Control registers UARTi transmit/receive control register 1 UART0 transmit/receive control register 1 (Address 35 UART1 transmit/receive control register 1 (Address 3D Functions Bit name At reset Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer Transmit buffer empty flag register.
Page 468 APPENDIX Appendix 3. Control registers Count start register b4 b3 Count start register (Address 40 Bit name Functions At reset 0 : Stop counting Timer A0 count start bit 1 : Start counting Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit...
Page 469 APPENDIX Appendix 3. Control registers Up-down register Up-down register (Address 44 Bit name Functions At reset 0 : Down-count Timer A0 up-down bit 1 : Up-count Timer A1 up-down bit This function is valid when the contents of the up-down register is Timer A2 up-down bit selected as the up-down switching Timer A3 up-down bit...
Page 470 APPENDIX Appendix 3. Control registers Timer Ai register (b15) (b8) Timer A0 register (Addresses 47 , 46 b0 b7 Timer A1 register (Addresses 49 , 48 Timer A2 register (Addresses 4B , 4A Timer A3 register (Addresses 4D , 4C Timer A4 register (Addresses 4F , 4E Functions...
Page 471 APPENDIX Appendix 3. Control registers Timer Mode (b15) (b8) Timer A0 register (Addresses 47 , 46 b0 b7 Timer A1 register (Addresses 49 , 48 Timer A2 register (Addresses 4B , 4A Timer A3 register (Addresses 4D , 4C Timer A4 register (Addresses 4F , 4E Functions At reset...
Page 472 APPENDIX Appendix 3. Control registers Event counter mode (b15) (b8) Timer A0 register (Addresses 47 , 46 Timer A1 register (Addresses 49 , 48 Timer A2 register (Addresses 4B , 4A Timer A3 register (Addresses 4D , 4C Timer A4 register (Addresses 4F , 4E At reset Functions...
Page 473 APPENDIX Appendix 3. Control registers One-shot pulse mode (b15) (b8) Timer A0 register (Addresses 47 , 46 b0 b7 Timer A1 register (Addresses 49 , 48 Timer A2 register (Addresses 4B , 4A Timer A3 register (Addresses 4D , 4C Timer A4 register (Addresses 4F , 4E Functions...
Page 474 APPENDIX Appendix 3. Control registers Pulse width modulation (PWM) mode <When operating as a 16-bit pulse width modulator> Timer A0 register (Addresses 47 , 46 (b15) (b8) b0 b7 Timer A1 register (Addresses 49 , 48 Timer A2 register (Addresses 4B , 4A Timer A3 register (Addresses 4D , 4C...
Page 475 APPENDIX Appendix 3. Control registers Timer Bi register (b15) (b8) b0 b7 Timer B0 register (Addresses 51 , 50 Timer B1 register (Addresses 53 , 52 Timer B2 register (Addresses 55 , 54 Functions At reset 15 to 0 These bits have different functions according Undefined to the operating mode.
Page 476 APPENDIX Appendix 3. Control registers Timer mode (b15) (b8) b0 b7 Timer B0 register (Addresses 51 , 50 Timer B1 register (Addresses 53 , 52 Timer B2 register (Addresses 55 , 54 At reset Functions 15 to 0 These bits can be set to “0000 ”...
Page 477 APPENDIX Appendix 3. Control registers Event counter mode (b15) (b8) Timer B0 register (Addresses 51 , 50 Timer B1 register (Addresses 53 , 52 Timer B2 register (Addresses 55 , 54 Functions At reset 15 to 0 These bits can be set to “0000 ”...
Page 478 APPENDIX Appendix 3. Control registers Pulse period/pulse width measurement mode (b15) (b8) b0 b7 Timer B0 register (Addresses 51 , 50 Timer B1 register (Addresses 53 , 52 Timer B2 register (Addresses 55 , 54 Functions At reset 15 to 0 The measurement result of pulse period or Undefined pulse width is read out.
Page 479 APPENDIX Appendix 3. Control registers Processor mode register 0 Processor mode register 0 (Address 5E Bit name Functions At reset b1 b0 Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not selected (Note 1) Fix this bit to “0.”...
Page 480 APPENDIX Appendix 3. Control registers Processor mode register 1 Processor mode register 1 (Address 5F Bit name Functions At reset 1, 0 Fix these bits to “0.” Clock source for peripheral divided by 2 devices select bit (Note) 0 : High-speed running CPU running speed select bit 1 : Low-speed running (Note)
Page 481 APPENDIX Appendix 3. Control registers Watchdog timer register Watchdog timer register (Address 60 Functions At reset – 7 to 0 Initializes the watchdog timer. Undefined When a dummy data is written to this register, the watchdog timer’s value is initialized to “FFF .”...
Page 482: Interrupt Control Register
APPENDIX Appendix 3. Control registers Interrupt control register A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 70 to 7C Bit name Functions At reset b2 b1 b0 Interrupt priority level select bits 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1...
Page 483 APPENDIX Appendix 4. Package outlines Appendix 4. Package outlines 80P6N-A 20–32 7751 Group User’s Manual...
Page 484 APPENDIX Appendix 4. Package outlines 80D0 7751 Group User’s Manual 20–33...
Page 485: Appendix 5. Example For Processing Unused Pins
APPENDIX Appendix 5. Example for processing unused pins Appendix 5. Example for processing unused pins Table 1 Example for processing unused pins in single-chip mode Pin name Example of processing Ports P0 to P8 Set for input mode and connect these pins to Vcc or Vss via a resistor;...
Page 486 APPENDIX Appendix 5. Example for processing unused pins Table 2 Example for processing unused pins in memory expansion mode or microprocessor mode Pin name Example of processing Ports P4 to P4 , P5 to P8 Set for input mode and connect these pins to Vcc or Vss via a resistor;...
Page 487 APPENDIX Appendix 5. Example for processing unused pins When setting ports for input mode P0–P8 –P4 , P5–P8 Left open Left open HLDA Left open H O LD BYTE R D Y In memory expansion mode In single-chip mode In microprocessor mode When setting ports for output mode P0–P8 Left open...
Page 488: Appendix 6. Hexadecimal Instruction Code Table
APPENDIX Appendix 6. Hexadecimal instruction code table Appendix 6. Hexadecimal instruction code tab le 7751 Group User’s Manual 20–37...
Page 489 APPENDIX Appendix 6. Hexadecimal instruction code table 20–38 7751 Group User’s Manual...
Page 490 APPENDIX Appendix 6. Hexadecimal instruction code table 7751 Group User’s Manual 20–39...
Page 491: Appendix 7. Machine Instructions
APPENDIX Appendix 7. Machine instructions Appendix 7. Machine instructions 20–40 7751 Group User’s Manual...
Page 492 APPENDIX Appendix 7. Machine instructions 7751 Group User’s Manual 20–41...
Page 493 APPENDIX Appendix 7. Machine instructions 20–42 7751 Group User’s Manual...
Page 494 APPENDIX Appendix 7. Machine instructions 7751 Group User’s Manual 20–43...
Page 495 APPENDIX Appendix 7. Machine instructions 20–44 7751 Group User’s Manual...
Page 496 APPENDIX Appendix 7. Machine instructions 7751 Group User’s Manual 20–45...
Page 497 APPENDIX Appendix 7. Machine instructions 20–46 7751 Group User’s Manual...
Page 498 APPENDIX Appendix 7. Machine instructions 7751 Group User’s Manual 20–47...
Page 499 APPENDIX Appendix 7. Machine instructions 20–48 7751 Group User’s Manual...
Page 500 APPENDIX Appendix 7. Machine instructions 7751 Group User’s Manual 20–49...
Page 501 APPENDIX Appendix 7. Machine instructions 20–50 7751 Group User’s Manual...
Page 502 APPENDIX Appendix 7. Machine instructions 7751 Group User’s Manual 20–51...
Page 503 APPENDIX Appendix 7. Machine instructions 20–52 7751 Group User’s Manual...
Page 504 APPENDIX Appendix 7. Machine instructions 7751 Group User’s Manual 20–53...
Page 505 APPENDIX Appendix 7. Machine instructions 20–54 7751 Group User’s Manual...
Page 506 APPENDIX Appendix 7. Machine instructions 7751 Group User’s Manual 20–55...
Page 507 APPENDIX Appendix 7. Machine instructions 20–56 7751 Group User’s Manual...
Page 508 APPENDIX Appendix 7. Machine instructions 7751 Group User’s Manual 20–57...
Page 509 APPENDIX Appendix 7. Machine instructions 20–58 7751 Group User’s Manual...
Page 510 APPENDIX Appendix 7. Machine instructions 7751 Group User’s Manual 20–59...
Page 511 APPENDIX Appendix 7. Machine instructions 20–60 7751 Group User’s Manual...
Page 512: Appendix 8. Examples Of Noise Immunity Improvement
APPENDIX Appendix 8. Examples of noise immunity improvement Appendix 8. Examples of noise immunity improvement Generally effective examples of noise immunity improvements are described below. Although the effect of these countermeasure depends on each system, refer to the following when an noise-related problem occurs.
Page 513 APPENDIX Appendix 8. Examples of noise immunity improvement (2) Wiring for clock input/output pins Make the length of wiring connected to the clock input/output pins as short as possible. Make the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator and Vss pin of the microcomputer, as short as possible (within 20 mm).
Page 514 APPENDIX Appendix 8. Examples of noise immunity improvement (4) Wiring for CNVss (V ) pin of built-in PROM version < In single-chip or memory expansion modes> Connect CNVss (V ) to Vss pin of the microcomputer with the shortest possible wiring. If the above countermeasure can not be taken, insert an approximate 5 kΩ...
Page 515 APPENDIX Appendix 8. Examples of noise immunity improvement 2. Connection of bypass capacitor between Vss and Vcc lines Connect an approximate 0.1 µ F bypass capacitor as follows: Connect a bypass capacitor between the Vss and Vcc pins, at equal lengths. The wiring connecting the bypass capacitor between the Vss and Vcc pins should be as short as possible.
Page 516 APPENDIX Appendix 8. Examples of noise immunity improvement 3. Wiring for analog input pins, analog power source pins, etc. (1) Processing analog input pins Connect a resistor to the analog signal line, which is connected to an analog input pin, and make the connection as close to the microcomputer as possible.
Page 517 APPENDIX Appendix 8. Examples of noise immunity improvement (2) Processing analog power source pins, etc. Use independent power sources for Vcc, AVcc and V pins. Insert capacitors between the AVcc and AVss pins, and between the V and AVss pins. Reasons: Prevents the A-D converter from noise on the Vcc line.
Page 518 APPENDIX Appendix 8. Examples of noise immunity improvement 4. Oscillator protection The oscillator which generates the basic clock for the microcomputer operations must be protected from the affect of other signals. (1) Distance oscillator from signal lines with large current flows Install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance.
Page 519 APPENDIX Appendix 8. Examples of noise immunity improvement (3) Oscillator protection using Vss pattern Print a Vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the oscillator mount position. Connect the Vss pattern to Vss pin of the microcomputer with the shortest possible wiring, separating it from other Vss patterns.
Page 520 APPENDIX Appendix 8. Examples of noise immunity improvement 5. Setup for I/O ports Setup I/O ports by hardware and software as follows: <Hardware protection> Connect a resistor of 100 ohms or more to an I/O port in series. <Software protection> As for an input port, read data several times for checking whether input levels are equal or not.
Page 521 APPENDIX Appendix 8. Examples of noise immunity improvement 6. Reinforcement of the power source line For the Vss and Vcc lines, use thicker wiring than that of other signal lines. When using a multilayer printed circuit board, the Vss and Vcc patterns must each be one of the middle layers.
Page 522: Appendix 9. Q & A
APPENDIX Appendix 9. Q & A Appendix 9. Q & A I n f o r m a t i o n w h i c h m a y b e h e l p f u l i n f u l l y u t i l i z i n g t h e 7 7 5 1 G r o u p i s p r o v i d e d i n Q &...
Page 523 APPENDIX Appendix 9. Q & A Interrupt If an interrupt request (b) occurs while executing an interrupt routine (a), is the main routine is not executed before the INTACK sequence for the next interrupt (b) is executed after the interrupt routine (a) under execution is completed? Sequence of execution...
Page 524 APPENDIX Appendix 9. Q & A Interrupt There is a routine where a certain interrupt request should not be accepted (with enabled acceptance of all other interrupt requests). Accordingly, the program set the interrupt priority level select bits of the interrupt to be not accepted to “000 ”...
Page 525 APPENDIX Appendix 9. Q & A Interrupt To prevent this problem, use software to execute the routine that should not accept a certain interrupt request after change of interrupt priority level is completed. The following shows a sample program. [ Sample program ] After an instruction which writes “000 ”...
Page 526 APPENDIX Appendix 9. Q & A Interrupt ____ Which timing of clock φ is the external interrupts (input signals to the INT pin) detected? ____ How can four or more external interrupt input pins (INT ) be used? (1) In both the edge sense and level sense, external interrupt requests occur when the input ____ pin changes its level regardless of clock φ...
Page 527 APPENDIX Appendix 9. Q & A Serial I/O (UART mode) ____ In the case selecting the CTS function in UART (clock asynchronous serial I/O) mode, when the ____ transmitting side check the CTS input level ? It is check near the middle of the stop bit (when two stop bits are selected, the second stop bit). Input level to CTS pin is checked near here.
Page 528 APPENDIX Appendix 9. Q & A Hold function ______ When “L” level is input to the HOLD pin, how long is the bus actually opened ? The bus is opened after 50 ns at maximum has passed from the rising edge of next clock φ when ____ the HLDA pin output becomes “L”...
Page 529 APPENDIX Appendix 9. Q & A Processor mode If the processor mode is switched as described below by using the processor mode bits (bits 1 and 0 at address 5E ) during program execution, is there any precaution in software? Single-chip mode →...
Page 530 APPENDIX Appendix 9. Q & A Is there any SFR for which instructions that can be used to set registers or bits are limited? Use the STA or LDM instruction to set the registers or the bits listed below. Do not use read- modify-write instructions (i.e., CLB, SEB, INC, DEC, ASL, ASR, LSR, ROL, and ROR).
Page 531 APPENDIX Appendix 9. Q & A Clock Is there any precaution when f(X ) > 25 MHz ? Set the processor mode register 1 (address 5F ) to the following. Fix these bits to “0.” Bus cycle when accessing external device b5 b4 0 0 : 5 φ...
Page 532 APPENDIX Appendix 9. Q & A Clock ) ≤ 25 MHz ? Is there any precaution when f(X When setting the CPU running speed select bit (bit 3 at address 5F ) to “1,” SFR and internal ROM access become faster than this bit is “0.” Accordingly, we recommend to set this bit to “1.”...
Page 533 APPENDIX Appendix 9. Q & A Substitute for 7700 Series/7750 Series Are there precautions when the 7751 Series substitutes for the 7700 Series or the 7750 Series? The common precautions are described below. Refer to the relevant chapter for details. •Fix the processor status register (PS) bits 15 to 11 to “0.”...
Page 534 APPENDIX Appendix 9. Q & A Watchdog timer When detecting the software runaway by the watchdog timer, if not software reset but setting the same value as the contents of the reset bector address to the watchdog timer interrupt bector address is processed, how does it result in? When branching to the reset branch address within the watchdog timer interrupt routine, how does it result in?
Page 535 APPENDIX Appendix 9. Q & A MEMORANDUM 20–84 7751 Group User’s Manual...
Page 536 GLOSSARY...
Page 537 GLOSSARY This section briefly explains the terms used in this user’s manual. The terms defined here apply to this manual only. Term Meaning Relevant term Access Means performing read, write, or read and write. Access space An accessible memory space of up to 16 Mbytes. Access Access characteristics Means whether accessible or not.
Page 538 GLOSSARY Term Meaning Relevant term Up-count Means increasing by 1 and counting. Down-count Wait mode A state where the oscillation circuit is operating, however, the Stop mode program execution is stopped. By executing the WIT instruction, the microcomputer enters Wait mode. 7751 Group User’s Manual...
Page 539 GLOSSARY MEMORANDUM 7751 Group User’s Manual...
Page 540 MITSUBISHI SEMICONDUCTORS USER’S MANUAL 7751 Group Jul. First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.

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7751 series

Renesas 7700 FAMILY User Manual

Chapter 1 . Description

Performance Overview

Pin Configuration

Pin Description

Block Diagram

Chapter 2. Central Processing Unit (Cpu)

Bus Interface Unit

Access Space

Memory Assignment

Processor Modes

Chapter 3 INPUT/OUTPUT PINS

Programmable I/O Ports

I/O Pins of Internal Peripheral Devices

Chapter 4. Interrupts

Overview

Interrupt Sources

Interrupt Control

Interrupt Priority Level

Interrupt Priority Level Detection Circuit

Interrupt Priority Level Detection Time

Sequence from Acceptance of Interrupt Request to Execution of Interrupt Routine

Return from Interrupt Routine

Multiple Interrupts

External Interrupts (INT

Chapter 5 . Timer a

Overview

Block Description

Timer Mode

Event Counter Mode

One-Shot Pulse Mode

Pulse Width Modulation (PWM) Mode

Chapter 6 . Timer B

Overview

Block Description

Timer Mode

Event Counter Mode

Pulse Period/Pulse Width Measurement Mode

Chapter 7 . Serial I/O

Overview

Block Description

Clock Synchronous Serial I/O Mode

Clock Asynchronous Serial I/O (UART) Mode

Chapter 8 . A-D Converter

Overview

Block Description

A-D Conversion Method (Successive Approximation Conversion Method)

Absolute Accuracy and Differential Non-Linearity Error

Comparison Voltage in 8-Bit Mode

One-Shot Mode

Repeat Mode

Single Sweep Mode

Repeat Sweep Mode 0

Repeat Sweep Mode 1

Chapter 9 . Watchdog Timer

Block Description

Operation Description

Precautions When Using Watchdog Timer

Chapter 10. Stop Mode

Clock Generating Circuit

Operation Description

Precautions for Stop Mode

Chapter 11. Wait Mode

Clock Generating Circuit

Operation Description

Precautions for Wait Mode

Chapter 12 . Connection with External Devices

Signals Required for Accessing External Devices

Bus Cycle

Ready Function

Hold Function

Chapter 13. Reset

Hardware Reset

Software Reset

Chapter 14 . Clock Generating Circuit

Oscillation Circuit Example

Clock

Chapter 15. Electrical Characteristics

Absolute Maximum Ratings

Electrical Characteristics