Renesas 7700 FAMILY User Manual page 296

Address
Count start register
40
16
41
16
42 One-shot start register
16
43
16
44
16
45
16
46
16
47
16
48
16
49
16
4A
16
4B
16
4C
16
4D
16
4E
16
4F
16
50
16
51
16
52
16
53
16
54
16
55
16
56
Timer A0 mode register
16
57
Timer A1 mode register
16
58
Timer A2 mode register
16
59
16 Timer A3 mode register
5A
16 Timer A4 mode register
5B
16 Timer B0 mode register
5C
Timer B1 mode register
16
5D
Timer B2 mode register
16
5E
Processor mode register 0
16
5F
Processor mode register 1
16
Notes 1: The access characteristics at addresses 46
mode. (Refer to "Chapter 5. TIMER A.")
2: The access characteristics at addresses 50
mode. (Refer to "Chapter 6. TIMER B.")
3: The access characteristics for bit 5 at addresses 5B
operating mode. (Refer to "Chapter 6. TIMER B.")
4: The access characteristics for bit 1 at address 5E
according to the voltage level supplied to the CNVss pin. (Refer to section "2.5 Processor
modes.")
Fig. 13.1.5 State of SFR and internal RAM areas immediately after reset (3)
Register name
b7
WO
Up-down register
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
RW
RW
RW
7751 Group User's Manual
Access characteristics
b0
RW
WO
RW
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
RW
RW
RW
RW
RW
RW
(Note 3)
RW
(Note 3)
RW
(Note 3)
RW WO RW RW
(Note 4)
RW
to 4F vary according to Timer A's operating
16 16
to 55 vary according to Timer B's operating
16 16
16
and its state immediately after a reset vary
16
13.1 Hardware reset
State immediately after a reset
b7
00
16
?
?
0
0
?
0 0
0 0 0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
00
16
00
16
00
16
00
16
00
16
? ?
0 0 0
0 0 ? ?
0
0 0 ? ? 0
0 0
0 0 0
0 0 0 0 0
to 5D vary according to Timer B's
16
RESET
b0
0 0
0
0 0 0
0 0 0
0 0 0
0 0 0
0
0
(Note 4)
0 0 0
13–7