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RESET
13.1 Hardware reset
Address
20
16
21
16
22
16
23
16
24
16
25
16
26
16
27
16
28
16
29
16
2A
16
2B
16
2C
16
2D
16
2E
16
2F
16
30
UART0 transmit/receive mode register
16
31
UART0 baud rate register
16
32
16
UART0 transmit buffer register
33
16
34
UART0 transmit/receive control register 0
16
35
UART0 transmit/receive control register 1
16
36
16
UART0 receive buffer register
37
16
38
UART1 transmit/receive mode register
16
39
UART1 baud rate register
16
3A
16
UART1 transmit buffer register
3B
16
3C
UART1 transmit/receive control register 0
16
3D
16
UART1 transmit/receive control register 1
3E
16
UART1 receive buffer register
3F
16
Fig. 13.1.4 State of SFR and internal RAM areas immediately after reset (2)
13–6
Register name
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
7751 Group User's Manual
Access characteristics
b7
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
WO
WO
RW
RO
RW
RW
RO
RO
RO
RW
WO
WO
RW
RO
RW
RO
RW
RO
RO
State immediately after a reset
b0
b7
?
0
0
0
0
0
?
0
0
0
0
0
?
0
0
0
0
0
?
0
0
0
0
0
?
0
0
0
0
0
?
0
0
0
0
0
?
0
0
0
0
0
?
0
0
0
0
0
00
16
?
?
?
WO
?
?
?
0
1
RW
0
0
0
0
0
?
0
0
0
0
0
RO
00
16
?
?
?
WO
?
?
?
0
1
RW
0
0
0
0
0
?
RO
0
0
0
0
0
b0
0
?
0
?
0
?
0
?
0
?
0
?
0
?
0
?
0
0
0
0
1
0
?
0
0
0
0
0
0
1
0
0
0
?
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