Renesas 7700 FAMILY User Manual page 444

Program verify command
Figure 19.2.4 shows the program verify command execution timing.
This command is executed to verify data of address where the program command has been
executed after executing the program command.
The command code "C0
When setting the OE signal to "L" level, data of address where the program command has been
executed is read out and latched to the internal data latch.
When returning the OE signal to "H" level and inputting the serial clock, the data which is latched
to the data latch is output externally.
Since the address is internally latched when the program command is executed, there is no need
to input it when the program verify command is executed.
SCLK
SDA
OE
BUSY
"L"
Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of
the serial clock. The SDA pin is switched in the floating state during the t
last rising edge of the serial clock (at the 8th bit).
Fig. 19.2.4 Program verify command execution timing
" is input at the first transfer.
16
___
___
0 0 0 0 0 0 1 1
Command code input (C0
16
t
CRPV
7751 Group User's Manual
FLASH MEMORY VERSION
19.2 Serial input/output mode
D
0
) Verify data output
t t
WR RC
Verify read
D
7
(Note)
period after the
h(C-E)
19–27