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APPLICATIONS
17.1 Memory expansion
(2) Writing data
Figure 17.1.7 shows the timing at which data is written to an external memory.
When writing data, the output data is validated after t
validated data is output continuously until t
lists the data of t
Data output at writing data must satisfy the data set up time, t
write to an external memory.
External memory
write signals
External memory
chip select signals
Address and data output
A
/D
–A
/D
8
8
15
15
A
/D
–A
/D
16
0
23
7
Fig. 17.1.7 Timing at which data is written to external memory
Table 17.1.4 Data of t
Bus cycle
Low-speed running
Parameter
t
d(E—P1Q)
t
d(E—P2Q)
t
h(E—P1Q)
1
t
hE—P2Q)
f(X
17–10
and the calculation formulas of t
d(E-P1Q/P2Q)
E
W, WE
CE, S
This applies when the external data bus has a width of 16 bits (BYTE = "L").
and calculation formulas of t
d(E-P1Q/P2Q)
Low-speed running
3 φ access
2 φ access
35
35
9
10
1
10
9
– 22
– 22
)
f(X
)
IN
IN
7751 Group User's Manual
d(E-P1Q/P2Q)
passes from rising of the E signal. Table 17.1.4
h(E-P1Q/P2Q)
t
w(EL)
t
d
(E-P1Q/P2Q)
Address
h(E-P1Q/P2Q)
Low-speed running
High-speed running
4 φ access
35
1
1
10
9
– 22
f(X
f(X
)
IN
passes from falling of the E signal. Its
_
.
h(E-P1Q/P2Q)
, and the data hold time, t
su(D)
t
h
(E-P1Q/P2Q)
Data
Address
t
h
(D)
t
su
(D)
: Specifications of the M37751
(The others are the external memory's.)
(unit: ns)
High-speed running
3 φ access
4 φ access
35
35
10
9
9
1
10
– 10
– 10
)
f(X
)
IN
IN
_
, for
h(D)
High-speed running
5 φ access
35
1
10
9
– 10
f(X
)
IN
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