Renesas 7700 FAMILY User Manual page 282

CONNECTION WITH EXTERNAL DEVICES
4 access in low-speed running, 4 access in high-speed running
5 access in high-speed running
Fig. 12.3.2 Timings of acceptance of Ready request and termination of Ready state (2)
Judgment timing of input level to RDY pin
Clock
1
BIU
CPU
E
ALE
RDY
Judgment timing of input level to RDY pin
Clock
1
BIU
CPU
E
ALE
RDY
By accepting an Ready request, "L" level of
by , and clocks
Ready state is terminated.
Input level to the
above .
Notes 1: The timing of ALE signal differs depending on low-speed running or high-speed running,
and accessing an internal area or an external area. For more information, refer to section
"Chapter 15. ELECTRICAL CHARACTERISTICS ."
2: The dotted lines of signals
the pin is "H", no Ready request.
RDY
7751 Group User's Manual
Term using bus
Term using bus
signal stops for 1 cycle with the clock
E
and stop at "L" level.
BIU CPU
pin is not judged during the term unusing the bus or before the condition
RDY
, and
BIU CPU
12.3 Ready function
E indicate the waveform when input level to
, indicated
1
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