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TIMER B
6.4 Event counter mode
6.4.1 Setting for event counter mode
Figure 6.4.2 shows an initial setting example for registers relevant to the event counter mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to section "Chapter 4.
INTERRUPTS."
Selecting event counter mode and count polarity
b7
Setting divide ratio
(b15)
b7
Fig. 6.4.2 Initial setting example for registers relevant to event counter mode
6–16
b0
0 1
Timer Bi mode register (i = 0 to 2) (Addresses 5B
Selection of event counter mode
Count polarity select bits
b3 b2
0 0 : Counts at falling of external signal.
0 1 : Counts at rising of external signal.
1 0 : Counts at both of falling and rising of external signal.
1 1 : Not selected.
(b8)
b0
b7
Setting interrupt priority level
b7
b0
Interrupt priority level select bits
When using interrupts, set these bits to level 1–7.
When disabling interrupts, set these bits to level 0.
Setting port P6 direction register
b7
b0
Setting count start bit to "1"
b7
7751 Group User's Manual
: It may be either "0" or "1."
b0
Timer B0 register (Addresses 51
Timer B1 register (Addresses 53
Timer B2 register (Addresses 55
Can be set to "0000
" to "FFFF
" (n).
16
16
Note: The counter divides the count source by n + 1.
Timer Bi interrupt control register (i = 0 to 2)
(Addresses 7A
to 7C
)
16
16
Port P6 direction register (Address 10
TB0
pin
IN
Clear the corresponding bit to "0."
TB1
pin
IN
TB2
pin
IN
b0
Count start register (Address 40
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
to 5D
)
16
16
, 50
)
16
16
, 52
)
16
16
, 54
)
16
16
)
16
)
16
Count starts
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