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4.6 Interrupt priority level detection time
After sampling had started, an interrupt priority level detection time has elapses before an interrupt request
is accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the
interrupt priority level detection time.
As the interrupt priority level detection time, normally select "2 cycles of internal clock φ ."
(1) Interrupt priority detection time select bits
b7
b6
b5
0
(2) Interrupt priority level detection time
Interrupt priority level
detection time
Note: Pulse exists when "2 cycles of
Fig. 4.6.1 Interrupt priority level detection time
b4
b3
b2
b1
b0
0
b5, b4
0 0
0 1
1 0
1 1
φ
Op code fetch cycle
Sampling pulse
(a) 7 cycles
(b) 4 cycles
(c) 2 cycles
φ
7751 Group User's Manual
4.6 Interrupt priority level detection time
Processor mode register 0 (Address 5E
Processor mode bits
Fix to "0."
Software reset bit
Interrupt priority detection time select bits
7 cycles of
[(a) shown below]
4 cycles of
[(b) shown below]
2 cycles of
[(c) shown below]
Not selected
Fix to "0."
φ
Clock
output select bit
1
(Note)
" is selected.
INTERRUPTS
16
4–13
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