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<When reading>
E
A
/D
–A
8
8
15
A
/D
–A
16
0
23
OC (F245), RD
External memory
data output A
(F245)
<When writing>
E
A
/D
–A
/D
8
8
15
A
/D
–A
/D
16
0
23
OC (F245), WO, WE
External memory
data output B
Fig. 17.1.14 Timing chart for sample circuit using bus buffers (at low–speed running-1)
/D
15
/D
7
15
7
(F245)
7751 Group User's Manual
135 (min.)
5 (max.)
A
BC32 (t
)
PHL
F245
(t
/t
PZH
PZL
135 (min.)
35 (max.)
A
BC32 (t
)
PHL
F245
(t
PHL
APPLICATIONS
17.1 Memory expansion
18 (min.)
BC32 (t
F245
)
(t
D
D
BC32 (t
F245
/t
)
(t
PLH
D
(Unit : ns)
A
)
PLH
/t
)
PHZ
PLZ
A
)
PLH
/t
)
PHZ
PLZ
17–19
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