Renesas 7700 FAMILY User Manual page 179

SERIAL I/O
7.3 Clock synchronous serial I/O mode
[When not using interrupts]
Checking state of UARTi transmit buffer register
UART0 transmit/receive control register 1 (Address 35 )
UART1 transmit/receive control register 1 (Address 3D )
b7
Writing of next transmit data
UART0 transmit buffer register (Address 32
UART1 transmit buffer register (Address 3A
b7
Fig. 7.3.2 Writing data after start of transmission
7–22
b0
b0
1
Transmit buffer empty flag
0: Data present in transmit buffer register
1: No data present in transmit buffer register
(Writing of next transmit data is possible.)
16
16
b0
Set transmit data here.
7751 Group User's Manual
[When using interrupts]
The UARTi transmit interrupt request
occurs when the UARTi transmit buffer
register becomes empty.
16
16
Note :
This figure shows the bits and registers required
for processing.
Refer to Figure 7.3.5 about the change of flag state
)
and the occurrence timing of an interrupt request.
)
UARTi transmit interrupt