Renesas 7200 Series User Manual
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Renesas 7200 Series User Manual

Mitsubishi 8-bit single-chip microcomputer
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Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003

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  • Page 1 Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.
  • Page 2 MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7200 SERIES 7220 Group User’s Manual...
  • Page 3 keep safety first in your circuit designs ! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
  • Page 4 Preface This manual describes the hardware of the Mitsubishi CMOS 8-bit microcomputers 7220 group. After reading this manual, the user should have a through knowledge of the functions and features of 7220 group, and should be able to fully utilize the product.
  • Page 5 BEFORE USING THIS MANUAL This user’s manual consists of the following chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. The M37221M6-XXXSP/FP is used as a general example in describing the functions of the 7220 group, unless other wise noted. 1.
  • Page 6 2. Register diagram The figure of each register structure describes its functions, contents at reset, end attributes as follows: Bit attributes Bits (Note 2) CPU Mode Register Values immediately after reset release (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) (CM) [Address FB Name Functions...

  • Page 7: Table Of Contents

    Table of contents Table of contents CHAPTER 1. OVERVIEW 1.1 Performance overview ......................1-2 1.2 Pin configuration ........................1-5 1.3 Pin description ........................1-7 1.4 Functional block diagram ....................1-9 CHAPTER 2. FUNCTIONAL DESCRIPTION 2.1 Central processing unit ....................... 2-2 2.1.1 Accumulator (A) ......................
  • Page 8 Table of contents Table of contents 2.7 Serial I/O ..........................2-40 2.7.1 Structure of serial I/O ....................2-40 2.7.2 Serial I/O register (address 00DD ) ................. 2-42 2.7.3 Clock source generating circuit ................. 2-42 2.7.4 Serial input/output common transmission/reception mode ........2-42 2.7.5 Serial I/O data receive method (when an internal clock is selected) ....
  • Page 9 Table of contents CHAPTER 4. M37220M3-XXXSP/FP 4.1 Performance overview ......................4-2 4.2 Pin configuration ........................4-4 4.3 Pin description ........................4-6 4.4 Functional block diagram ....................4-8 4.5 Functional description ......................4-9 4.5.1 Access area ........................4-10 4.5.2 Memory assignment ..................... 4-11 4.5.3 Input/Output pins ......................
  • Page 10 Table of contents CHAPTER 6. APPENDIX 6.1 Package outline ........................6-2 6.2 Termination of unused pins ....................6-3 6.3 Notes on use ......................... 6-4 6.3.1 Notes on processor status register ................6-4 6.3.2 Notes on decimal operation ..................6-5 6.3.3 Notes on Interrupts ......................6-5 6.3.4 Notes on serial I/O ......................
  • Page 11 List of figures List of figures CHAPTER 1. OVERVIEW Fig. 1.2.1 Pin configuration (top view) (1) ................. 1-5 Fig. 1.2.2 Pin configuration (top view) (2) ................. 1-6 Fig. 1.4.1 Functional block diagram .................... 1-9 CHAPTER 2. FUNCTIONAL DESCRIPTION Fig. 2.1.1 Registers configuration diagram ................2-2 Fig.
  • Page 12 List of figures Fig. 2.8.1 Block diagram of multi-masteer I C-BUS interface ..........2-48 Fig. 2.8.2 I C data shift register ....................2-49 Fig. 2.8.3 I C address register ....................2-50 Fig. 2.8.4 I C clock control register ..................2-52 Fig.
  • Page 13 List of figures Fig. 2.15.1 Timing diagram at reset ..................2-95 Fig. 2.15.2 Internal state immediately after reset (1) ............. 2-96 Fig. 2.15.3 Internal state immediately after reset (2) ............. 2-97 Fig. 2.15.4 Internal state immediately after reset (3) (only M37221M8/MA-XXXSP) ..2-98 Fig.
  • Page 14 List of figures Fig. 5.1.10 Flowchart of CRT interrupt processing routine (when setting multiple interrupts) ................5-11 Fig. 5.1.11 Flowchart of V interrupt processing routine SYNC (when setting multiple interrupts) ................5-12 Fig. 5.2.1 Color register n (M37221ERSS) ................5-13 Fig.
  • Page 15 List of figures Fig. 6.4.1 Wiring for RESET input pin ..................6-11 Fig. 6.4.2 Wiring for clock I/O pin ..................... 6-11 Fig. 6.4.3 Wiring for CNV pin ....................6-12 Fig. 6.4.4 Wiring for V pin of One Time PROM and EPROM version ......6-12 Fig.
  • Page 16 List of figures Fig. 6.7.28 Interrupt request register 1 ..................6-48 Fig. 6.7.29 Interrupt request register 2 ..................6-49 Fig. 6.7.30 Interrupt control register 1 ..................6-49 Fig. 6.7.31 Interrupt control register 2 ..................6-50 Fig. 6.7.32 ROM correction enable register ................6-50 Fig.
  • Page 17 List of tables List of tables CHAPTER 1. OVERVIEW Table 1.1.1 Performance overview (1) ..................1-3 Table 1.1.2 Performance overview (2) ..................1-4 Table 1.3.1 Pin description (1) ....................1-7 Table 1.3.2 Pin description (2) ....................1-8 CHAPTER 2. FUNCTIONAL DESCRIPTION Table 2.2.1 Zero page addressing ....................
  • Page 18 List of tables CHAPTER 4. M37220M3-XXXSP/FP Table 4.1.1 Performance overview (1) ..................4-2 Table 4.1.2 Performance overview (2) ..................4-3 Table 4.3.1 Pin description (1) ....................4-6 Table 4.3.2 Pin description (2) ....................4-7 Table 4.5.1 Difference between M37220M3-XXXSP/FP and M37221M6-XXXSP/FP ... 4-9 Table 4.5.2 Difference of programmable ports between M37221M6-XXXSP/FP and M37220M3-XXXSP/FP ...................

  • Page 19: Performance Overview

    C H A P T E R 1 OVERVIEW 1.1 Performance overview 1.2 Pin configuration 1.3 Pin description 1.4 Functional block diagram...
  • Page 20 OVERVIEW 1.1 Performance overview 1.1 Performance overview The 8-bit microcomputers: -M37221M4-XXXSP -M37221M6-XXXSP/FP -M37221M8-XXXSP -M37221MA-XXXSP -M37220M3-XXXSP/FP have their simple instruction set; the ROM, RAM, and I/O addresses are placed on the same memory map to enable easy programming. Furthermore, they have many additional functions for tuning system for TV: PWM output (14-bit and 8-bit) CRT display A-D comparator (resistance string method)

  • Page 21: Chapter 1. Overview

    OVERVIEW 1.1 Performance overview The performance overview is shown in Table 1.1.1. M37220M3-XXXSP/FP Refer to “CHAPTER 4. M37220M3-XXXSP/FP.” Table 1.1.1 Performance overview (1) Parameter Performance Number of basic instructions 0.5 µ s (the minimum instruction execution time, at 8 Instruction execution time MHz oscillation frequency) Clock frequency 8 MHz (maximum)

  • Page 22: Table 1.1.2 Performance Overview (2)

    OVERVIEW 1.1 Performance overview Table 1.1.2 Performance overview (2) Parameter Performance Subroutine nesting 96 levels (maximum) M37221M4-XXXSP M37221M6-XXXSP/FP 128 levels (maximum) M37221M8-XXXSP M37221MA-XXXSP Interrupt External interrupt 3, Internal timer interrupt 4, Serial I/O interrupt 1, CRT interrupt 1, Multi-master I BUS interface interrupt 1, f(X )/4096 interrupt...

  • Page 23: Fig. 1.2.1 Pin Configuration (Top View) (1)

    OVERVIEW 1.2 Pin configuration 1.2 Pin configuration The pin configurations are shown in Figures 1.2.1 and 1.2.2. M37220M3-XXXSP/FP Refer to “CHAPTER 4. M37220M3-XXXSP/FP.” SYNC SYNC /PWM0 /PWM1 /OUT1 /PWM2 /PWM3 /PWM4 /PWM5 /OUT2 /INT2/A-D4 /SCL1 /SCL2 /INT1 /SDA1 /TIM3 /SDA2 /TIM2 /A-D1/INT3 /A-D2...

  • Page 24: Fig. 1.2.2 Pin Configuration (Top View) (2)

    OVERVIEW 1.2 Pin configuration SYNC SYNC /PWM0 /PWM1 /OUT1 /PWM2 /PWM3 /PWM4 /PWM5 /OUT2 /INT2/A-D4 /SCL1 /SCL2 /INT1 /SDA1 /TIM3 /SDA2 /TIM2 /A-D1/INT3 /A-D2 /A-D3 /A-D5 /A-D6 RESET OSC1/P3 OSC2/P3 Outline 42P2R-A Fig. 1.2.2 Pin configuration (top view) (2) 7220 Group User’s Manual...

  • Page 25: Table 1.3.1 Pin Description (1)

    OVERVIEW 1.3 Pin description 1.3 Pin description The pin description is shown in Table 1.3.1. M37220M3-XXXSP/FP Refer to “CHAPTER 4. M37220M3-XXXSP/FP.” Table 1.3.1 Pin description (1) Input/ Name Functions Output Power source Apply voltage of 5 V ± 10 % (typical) to V , and 0 V to V Connected to V ______...

  • Page 26: Table 1.3.2 Pin Description (2)

    OVERVIEW 1.3 Pin description Table 1.3.2 Pin description (2) Input/ Name Functions Output I/O port P2 Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. External clock Input Pins P2 , P2...
  • Page 27 OVERVIEW 1.4 Functional block diagram 1.4 Functional block diagram The functional block diagram is shown in Figure 1.4.1. M37220M3-XXXSP/FP Refer to “CHAPTER 4. M37220M3-XXXSP/FP.” 7220 Group User’s Manual...

  • Page 28: Chapter 2. Functional Description

    C H A P T E R 2 FUNCTIONAL DESCRIPTION 2.1 Central processing unit 2.2 Access area 2.3 Memory assignment 2.4 Input/Output pins 2.5 Interrupts 2.6 Timers 2.7 Serial I/O 2.8 Multi-master I C-BUS interface 2.9 A-D comparator 2.10 PWM 2.11 CRT display function 2.12 ROM correction function 2.13 Software runaway detect function...

  • Page 29: Accumulator (A)

    FUNCTIONAL DESCRIPTION 2.1 Central processing unit 2.1 Central processing unit The CPU of the M37221M6-XXXSP/FP has six main registers. The program counter (PC) is a 16-bit register consists of PC and PC , both of which are 8-bit registers. The other five registers: the accumulator (A), index register X (X), index register Y (Y), stack pointer (S) and processor status register (PS), all have an 8-bit configuration.

  • Page 30: Fig. 2.1.2 Cpu Mode Register

    FUNCTIONAL DESCRIPTION 2.1 Central processing unit 2.1.3 Stack pointer (S) The stack pointer is an 8-bit register used for interrupts and subroutine calls. The stack area can be assigned into the internal RAM. The internal RAM of M37221M6-XXXSP/FP is assigned in the zero page and the page 1. The both area can use for the stack area.

  • Page 31: Chapter 2. Functional Description

    FUNCTIONAL DESCRIPTION 2.1 Central processing unit Storing of the processor status register in items above is not performed during a subroutine call. Execute the PHP instruction in a program to push the processor status register onto a stack. To prevent data from losing during interrupts and subroutine calls, push the other registers onto a stack by software as described above.

  • Page 32: Fig. 2.1.3 Sequence Of Push Onto/Pop From A Stack During Interrupts And Subroutine Calls

    FUNCTIONAL DESCRIPTION 2.1 Central processing unit On-going routine • • • • • • • • Interrupt request M(S) (S)–1 M(S) Execute JSR (S)–1 M(S) (PS) M(S) (S)–1 (S)–1 • • • • • • • • Interrupt routine M(S) •...
  • Page 33 FUNCTIONAL DESCRIPTION 2.1 Central processing unit 2.1.4 Program counter (PC) The program counter is a 16-bit counter consists of PC and PC , both of which are 8-bit registers. The program counter indicates the address of the program to be executed next. The M37221M6-XXXSP/FP uses the stored program system.

  • Page 34: Fig. 2.1.4 Contents Of Stack After Execution Of Brk Instruction

    FUNCTIONAL DESCRIPTION 2.1 Central processing unit =B Flag PS (processor status register) (low-order of program counter) (high-order of program counter) Fig. 2.1.4 Contents of stack after execution of BRK instruction (6) X modified operation mode flag (T) ....Bit 5 This flag determines whether arithmetic operations are performed via the accumulator or directly between memories.

  • Page 35: Access Area

    FUNCTIONAL DESCRIPTION 2.2 Access area 2.2 Access area The ROM, RAM and various I/O control registers are assigned within the same memory area. Therefore, the same instructions are used for data transfers and arithmetic operations without making any distinction between memory and I/O. Since the program counter is a 16-bit register, 64 K-byte memory area can be accessed: from addresses as 0000 to FFFF...

  • Page 36: Fig. 2.2.2 Access Area Of M37221M8-Xxxsp And M37221Ma-Xxxsp

    FUNCTIONAL DESCRIPTION 2.2 Access area 0000 10000 Internal RAM Zero page 00C0 SFR area (640 bytes) (512 bytes) Special function register for display CRT display ROM 00FF (Refer to Figures 2. 3. 3 to 2. 3. 5) (8 K bytes) M37221MA M37221M8 Internal RAM...

  • Page 37: Zero Page (Addresses 0000 To 00Ff )

    FUNCTIONAL DESCRIPTION 2.2 Access area 2.2.1 Zero page (addresses 0000 to 00FF Table 2.2.1 Zero page addressing The 256 bytes from address 0000 to address 00FF Bytes required Addressing mode are called “zero page”. Zero page The internal RAM, I/O ports, timer, serial I/O, A-D Zero page Indirect comparison, PWM output, CRT display and interrupt Zero page X...

  • Page 38: Memory Assignment

    FUNCTIONAL DESCRIPTION 2.3 Memory assignment 2.3 Memory assignment Figures 2.3.1 and 2.3.2 show the memory assignment. The ROM, RAM and I/O assigned in this memory area are described below. M37220M3-XXXSP/FP Refer to “CHAPTER 4. M37220M3-XXXSP/FP.” Hexadecimal notation Decimal notation 10000 65536 0000 CRT display ROM...

  • Page 39: Fig. 2.3.2 Memory Assignment Of M37221M8-Xxxsp And M37221Ma-Xxxsp

    FUNCTIONAL DESCRIPTION 2.3 Memory assignment Decimal notation Hexadecimal notation 10000 65536 0000 Internal RAM Zero page SFR area 00C0 CRT display ROM (640 bytes) (512 bytes) Special function register for display (8 K bytes) 00FF (Refer to Figures 2. 3. 3 to 2. 3. 5) 0100 M37221MA M37221M8...

  • Page 40: Fig. 2.3.3 Memory Map Of Sfr (Special Function Register) (1)

    FUNCTIONAL DESCRIPTION 2.3 Memory assignment SFR Area (addresses C0 to DF Bit allocation State immediately after reset < > < > : “0” immediately after reset Function bit : “1” immediately after reset Name No function bit : Indeterminate immediately after reset : Fix this bit to “0”...

  • Page 41: Fig. 2.3.4 Memory Map Of Sfr (Special Function Register) (2)

    FUNCTIONAL DESCRIPTION 2.3 Memory assignment SFR Area (addresses E0 to FF Bit allocation State immediately after reset < > < > : “0” immediately after reset Function bit : “1” immediately after reset Name No function bit : Indeterminate immediately after reset : Fix this bit to “0”...

  • Page 42: Fig. 2.3.5 Memory Map Of 2 Page Register (Only M37221M8-Xxxsp And M37221Ma-Xxxsp)

    FUNCTIONAL DESCRIPTION 2.3 Memory assignment 2 Page Register Area (addresses 217 to 21B Bit allocation State immediately after reset < > < > : “0” immediately after reset Function bit : “1” immediately after reset Name No function bit : Indeterminate immediately after reset : Fix this bit to “0”...

  • Page 43: Internal Ram

    FUNCTIONAL DESCRIPTION 2.3 Memory assignment 2.3.1 Internal RAM The static RAM is assigned. The internal RAM is used as a stack area for subroutine calls and interrupts as well as for storing data. Both zero page and page 1 are used as a stack area. At reset, the page 1 is specified automatically. Ordinary, the stack pointer is set to the highest address in the internal RAM of the page 1 during initialization immediately after power on.

  • Page 44: Registers (Addresses 00Ce And 00Cf )

    FUNCTIONAL DESCRIPTION 2.3 Memory assignment 2.3.3 DA registers (addresses 00CE and 00CF The DA-H register is assigned to address 00CE , and the DA-L register is assigned to address 00CF Both registers consist of 8 bits. The DA-H register is used to set the high-order 8 bits of 14-bit PWM output data. The DA-L register is used to set the low-order 6 bits of 14-bit PWM output data (set to bits 0 to 5).

  • Page 45: A-D Control Register (Addresses 00Ee And 00Ef )

    FUNCTIONAL DESCRIPTION 2.3 Memory assignment (4) Border selection register (address 00E5 The border selection register is assigned to address 00E5 . This register consists of 8 bits, and is used to set the border for blocks 1 and 2 by using one bit each. Bits 1 and 3 to 7 are not used. (5) Color registers (addresses 00E6 to 00E9 Color registers 0 to 3 are assigned to addresses 00E6...

  • Page 46: Timer Mode Registers (Address 00F4 )

    FUNCTIONAL DESCRIPTION 2.3 Memory assignment 2.3.11 Timer mode registers (address 00F4 and 00F5 The timer 12 mode register is assigned to address 00F4 and the timer 34 mode register is assigned to address 00F5 . Both registers consist of 8 bits. They select the count source of timer and control the count stop bit.

  • Page 47: Input/Output Pins

    FUNCTIONAL DESCRIPTION 2.4 Input/Output pins 2.4 Input/Output pins The M37221M6-XXXSP/FP has 33 programable ports (I/O ports, input ports, output ports). The double- function ports function as ports and as pins for internal peripheral devices. M37220M3-XXXSP/FP Refer to “CHAPTER 4. M37220M3-XXXSP/FP.” Double-function ports ....
  • Page 48 FUNCTIONAL DESCRIPTION 2.4 Input/Output pins (2) Port P1 Port P1 is an 8-bit I/O port. The output structure is CMOS output, however, only when ports P1 – are used as multi-master I C-BUS interface, the output structure is N-channel open-drain output. Port P1 has basically the same function as port P0.

  • Page 49: Table 2.4.1 List Of Programmable Port Functions

    FUNCTIONAL DESCRIPTION 2.4 Input/Output pins Table 2.4.1 List of programmable port functions Ports Functions except port Name –P0 PWM0–PWM5 PWM output pin INT2/A-D4 External interrupt input pin/Analog input pin INT1 External interrupt input pin OUT2 CRT output pin SCL1 Multi-master I C-BUS interface pin SCL2 Multi-master I...

  • Page 50: Dedicated Pins

    FUNCTIONAL DESCRIPTION 2.4 Input/Output pins 2.4.2 Dedicated pins (1) 14-bit PWM output (D-A) pin This is a 14-bit PWM signal output pin. This pin also can be used for 1-bit general-purpose output port. The output structure is CMOS output. (2) Vertical and horizontal synchronous signal input pins (V SYNC SYNC These pins input the vertical and horizontal synchronous signals for CRT display.

  • Page 51: Fig. 2.4.1 I/O Pin Block Diagram (1)

    FUNCTIONAL DESCRIPTION 2.4 Input/Output pins /PWM0–P0 /PWM5, P3 N-channel open-drain output Direction register Data bus Port latch /OUT2, P1 /SCL1, P1 /SCL2, P1 /SDA1, P1 /SDA2, P1 /A-D1/INT3, P1 /A-D2, P1 /A-D3, , P2 , P2 , P2 /TIM3, P2 /TIM2, P2 –P2 , P3...

  • Page 52: Fig. 2.4.2 I/O Pin Block Diagram (2)

    FUNCTIONAL DESCRIPTION 2.4 Input/Output pins /OSC1, P3 Input Internal circuit D-A, P5 /R, P5 /G, P5 /B, P5 /OUT1 CMOS output Internal circuit SYNC SYNC Schmidt input SYNC SYNC indicates a pin. Fig. 2.4.2 I/O pin block diagram (2) 7220 Group User’s Manual 2-25...

  • Page 53: Interrupts

    FUNCTIONAL DESCRIPTION 2.5 Interrupts 2.5 Interrupts Interrupts are used in the following cases. When there is a request to execute a higher priority routine than current processing routine. When it is necessary to process according to a certain timing. The M37221M6-XXXSP/FP has 14 interrupt sources (including reset). These are vector interrupts with a fixed priority sequence.

  • Page 54: Interrupt Sources

    FUNCTIONAL DESCRIPTION 2.5 Interrupts 2.5.1 Interrupt sources The following explains interrupt sources, in order of priority (except reset). (1) CRT interrupt When displaying a character block with the CRT display function, the CRT interrupt request occurs at the completion of the display. (2) INT2 interrupt An INT2 interrupt request is generated by detecting a level transition on pin INT2 (external interrupt input).
  • Page 55 FUNCTIONAL DESCRIPTION 2.5 Interrupts (7) Timer 3 interrupt Timer 3 value is counted down. Timer 3 interrupt request occurs when the count source next to “00 ” is input. (8) Timer 2 interrupt Timer 2 value is counted down. Timer 2 interrupt request occurs when a count source next to “00 ”...

  • Page 56: Interrupt Control

    FUNCTIONAL DESCRIPTION 2.5 Interrupts 2.5.2 Interrupt control Each interrupt can be controlled with the interrupt request bit, the interrupt control bit, and the interrupt disable flag. Interrupt request bit Interrupt enable bit Start of Interrupt disable flag (I) interrupt Reset process BRK instruction Fig.
  • Page 57 FUNCTIONAL DESCRIPTION 2.5 Interrupts Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC Name Functions After reset R W 0 : No interrupt request issued Timer 1 interrupt 1 : Interrupt request issued request bit (TM1R) 1 Timer 2 interrupt...
  • Page 58 FUNCTIONAL DESCRIPTION 2.5 Interrupts Interrupt Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE Name Functions After reset R W Timer 1 interrupt 0 : Interrupt disabled enable bit (TM1E) 1 : Interrupt enabled Timer 2 interrupt 0 : Interrupt disabled enable bit (TM2E)

  • Page 59: Fig. 2.5.7 Interrupt Input Polatiry Register (Address 00F9 16 )

    FUNCTIONAL DESCRIPTION 2.5 Interrupts Interrupt Input Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt input polarity register(RE) [Address 00F9 Name Functions After reset Indeterminate Nothing is assigned. This bit is a write disable bit. R — When this bit is read out, the value is “0.” 1, 2 Fix these bits to “0.”...

  • Page 60: Fig. 2.5.9 Interrupt Control System

    FUNCTIONAL DESCRIPTION 2.5 Interrupts Interrupt request bits are set to “1” by occurrence of an interrupt request, even if the interrupt is disabled. Therefore, to disable interrupt processing, clear the interrupt request bit to “0” immediately before the interrupt disable state is cancelled (interrupt enable state, i.e., the interrupt enable bit = “1” and the interrupt disable flag = “0”).

  • Page 61: Timers

    FUNCTIONAL DESCRIPTION 2.6 Timers 2.6 Timers M37221M6-XXXSP/FP has four 8-bit timers with reload latch. Figure 2.6.1 shows the timer block diagram. Data bus Timer 1 latch (8) 1/4096 Timer 1 Timer 1 (8) interrupt request T12M0 T12M2 T12M4 Timer 2 latch (8) Timer 2 /TIM2 Timer 2 (8)

  • Page 62: Timer Functions

    FUNCTIONAL DESCRIPTION 2.6 Timers 2.6.1 Timer functions There are four timers; Timer 1, Timer 2, Timer 3, Timer 4 and each timer has an 8-bit reload latch. All timers are the count-down type, and when the timer latch value is “n”, the divide ratio is 1/(n+1)(“n” = 0 to 255).

  • Page 63: Fig. 2.6.3 Timer 12 Mode Register (Address 00F4 16 )

    FUNCTIONAL DESCRIPTION 2.6 Timers Timer 12 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Timer 12 mode register (T12M) [Address 00F4 Name Functions After reset Timer 1 count source 0: f(X )/16 selection bit (T12M0) 1: f(X )/4096 0: Internal clock Timer 2 count source 1: External clock from...

  • Page 64: Fig. 2.6.4 Timer 34 Mode Register (Address 00F5 16 )

    FUNCTIONAL DESCRIPTION 2.6 Timers Timer 34 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M) [Address 00F5 Name Functions After reset R W 0: f(X )/16 Timer 3 count source 1: External clock selection bit (T34M0) 0: Timer 3 overflow Timer 4 internal count 1: f(X...

  • Page 65: Fig. 2.6.5 Example Of Timer System

    FUNCTIONAL DESCRIPTION 2.6 Timers T12M4 T12M1 T12M0 “1” “1” Timer 2 Timer 1 Timer 1 Timer 2 interrupt interrupt 1/16 request request “0” “0” T12M2 T12M3 T12M4 T12M1 T12M0 “1” “1” Timer 1 Timer 2 Timer 1 Timer 2 interrupt interrupt 1/4096 request...

  • Page 66: Table 2.6.2 Contents Of Timers 3 And 4 When Reset Or When Executing Stp Instruction

    FUNCTIONAL DESCRIPTION 2.6 Timers 2.6.2 Timer 3 and timer 4 when reset and when executing the STP instruction Timers 3 and 4 start counting down immediately after reset status is released or stop mode is released, and CPU starts operating by supplying the internal clock φ at overflow of these timers. Therefore, the program can start under a stable clock.

  • Page 67: Serial I/O

    FUNCTIONAL DESCRIPTION 2.7 Serial I/O 2.7 Serial I/O The M37221M6-XXXSP/FP has on-chip clock synchronous serial I/O which can receive and transmit 8-bit data serially. Because pin S also can be used as the serial I/O data input pin, it can transmit and receive with only one signal line.

  • Page 68: Fig. 2.7.1 Serial I/O Block Diagram

    FUNCTIONAL DESCRIPTION 2.7 Serial I/O Data bus Frequency divider 1/16 Selection gate : Connected to black Synchronous circuit side at reset. Clock source SM : Serial I/O mode register generating circuit latch Serial I/O interrupt Serial I/O counter (8) request latch SM5 : LSB Serial I/O shift register (8)

  • Page 69: Clock Source Generating Circuit

    FUNCTIONAL DESCRIPTION 2.7 Serial I/O 2.7.2 Serial I/O register (address 00DD The serial I/O register is serial-parallel conversion register used for data transfer. This register consists of 8-bit and can be used as both transmit and receive register. Serial I/O register is assigned to address 00DD Although data transfer is performed bit by bit, it is possible to specify whether the data is transferred beginning with most-significant-bit (MSB) or least-significant-bit (LSB) by using bit 5 of the serial I/O mode register.

  • Page 70: Serial I/O Data Receive Method (When An Internal Clock Is Selected)

    FUNCTIONAL DESCRIPTION 2.7 Serial I/O 2.7.5 Serial I/O data receive method (when an internal clock is selected) (1) Initialization First, set the serial I/O mode register (address 00DC ) as follows. Select the synchronous clock (SM2 = “1,” SM1, SM0). Set P2 as pin S (SM3 = “1”).

  • Page 71: Serial I/O Data Transmit Method (When An External Clock Is Selected)

    FUNCTIONAL DESCRIPTION 2.7 Serial I/O 2.7.6 Serial I/O data transmit method (when an external clock is selected) (1) Initialization First, set the serial I/O mode register (address 00DC ) as follows. Select the synchronous clock (SM2 = “0”). Set P2 as pin S (SM3 = “1”).

  • Page 72: Note When Selecting A Synchronous Clock

    FUNCTIONAL DESCRIPTION 2.7 Serial I/O 2.7.7 Note when selecting a synchronous clock Regardless of either an internal or external clock is selected as the serial I/O synchronous clock source, the interrupt request bit is set to “1” after 8 transfer clocks. However, the serial I/O register contents will continue to be shifted as long as the transfer clock is being input to the serial I/O circuit, so it is necessary to stop after 8 transfer clocks.

  • Page 73: Fig. 2.7.7 Connection Example For Serial I/O Transmit/Receive

    FUNCTIONAL DESCRIPTION 2.7 Serial I/O The transmit side in Figure 2.7.7, P2 is set as the serial I/O data output pin and P2 is set as the serial I/O synchronous clock output pin by the initialization program. The receive side, P2 is set as the serial I/O data input pin and P2 is used for the serial I/O synchronous clock (external clock) input pin by the initialization program.

  • Page 74: Multi-Master I C-Bus Interface

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface 2.8 Multi-master I C-BUS interface The multi-master I C-BUS interface is a serial communications circuit, conforming to the Philips I C-BUS data transfer format. This interface, offering both an arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications.

  • Page 75: Construction Of Multi-Master I

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface I C address register Interrupt Interrupt SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW generating request signal circuit (IICIRQ) Address comparator Serial Noise Data data elimination control (SDA) circuit circuit I C data shift register AL AAS AD0 LRB MST TRX BB PIN I C status...

  • Page 76: Multi-Master I C-Bus Interface-Related Registers

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface 2.8.2 Multi-master I C-BUS interface-related registers (1) I C data shift register (S0: address 00D7 The I C data shift register (S0 : address 00D7 ) is an 8-bit shift register to store receive data and write transmit data.

  • Page 77: Fig. 2.8.3 I C Address Register

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface (2) I C address register (S0D: address 00D8 The I C address register (address 00D8 ) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected.
  • Page 78 FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface (3) I C clock control register (S2: address 00DB The I C clock control register (address 00DB ) is used to set ACK control, SCL mode and SCL frequency. Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency.

  • Page 79: Fig. 2.8.4 I C Clock Control Register

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 C clock control register (S2 : address 00DB Name Functions After reset R W SCL frequency control bits Setup value of Standard clock High speed (CCR0 to CCR4)

  • Page 80: Fig. 2.8.5 Connection Port Control By Bsel0 And Bsel1

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface (4) I C Control Register (S1D: address 00DA The I C control register (address 00DA ) controls the data communication format. Bits 0 to 2: Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted.

  • Page 81: Fig. 2.8.6 I C Control Register

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface C Control Register b7 b6 b5 b4 b3 b2 b1 b0 C control register (S1D : address 00DA Name Functions After reset R W Bit counter b2 b1 b0 (Number of transmit/recieve 0 : 8 bits) 1 : 7 (BC0 to BC2)
  • Page 82 FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface (5) I C status register (S1: address 00D9 The I C status register (address 00D9 ) controls the I C-BUS interface status. The low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation.
  • Page 83 FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface Bit 4: I C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU.

  • Page 84: Fig. 2.8.7 Interrupt Request Signal Generating Timing

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master.

  • Page 85: Start Condition, Stop Condition Generation Method

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface 2.8.3 START condition, STOP condition generation method (1) START condition generation method When the ESO bit of the I C control register (address 00DA ) is “1,” execute a write instruction to the I C status register (address 00D9 ) to set the MST, TRX and BB bits to “1.”...

  • Page 86: Fig. 2.8.11 Start Condition/Stop Condition Detect Timing Diagram

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface (3) START/STOP condition detect conditions The START/STOP condition detect conditions are shown in Figure 2.8.11 and Table 2.8.3. Only when the 3 conditions of Table 10 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ”...

  • Page 87: Fig. 2.8.12 Address Data Communication Format

    FUNCTIONAL DESCRIPTION 2.8 Multi-master I C-BUS interface (4) Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below. 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I C control register (address 00DA ) to “0.”...

  • Page 88: A-D Comparator

    FUNCTIONAL DESCRIPTION 2.9 A-D comparator 2.9 A-D comparator The M37221M6-XXXSP/FP has A-D comparator consists of the 6-bit D-A converter by resistance string method and a comparator. Figure 2.9.1 shows the A-D comparator block diagram. Data bus A-D control register 1 Comparator control Bits 0 to 2 A-D control...

  • Page 89: Table 2.9.1 Relationship Between Contents Of A-D Control Register 2 And Reference

    FUNCTIONAL DESCRIPTION 2.9 A-D comparator Table 2.9.1 Relationship between contents of A-D control register 2 and reference voltage “V ” A-D control register 2 Internal analog voltage (comparison voltage V bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1/128V 3/128V...

  • Page 90: Pwm

    FUNCTIONAL DESCRIPTION 2.10 PWM 2.10 PWM The M37221M6-XXXSP/FP has one 14-bit PWM (pulse width modulator) [DA], and six 8-bit PWM [PWM0– PWM5]. Table 2.10.1 shows the PWM function performance. Table 2.10.1 PWM function performance (at oscillation frequency = 8 MHz) Performance 14-bit PWM [DA] 8-bit PWM...

  • Page 91: 8-Bit Pwm Registers (Addresses 00D0 To 00D4 And 00F6 /Da Registers (Addresses 00Ce And 00Cf )

    FUNCTIONAL DESCRIPTION 2.10 PWM Data bus PWM timing generating circuit PWM register (Address : 00D0 PWM0 8-bit PWM circuit PWM1 PWM1 register (Address : 00D1 PWM2 PWM2 register (Address : 00D2 Selection gate : Connected to PWM3 black side when reset.

  • Page 92: 14-Bit Pwm (Da Output)

    FUNCTIONAL DESCRIPTION 2.10 PWM 2.10.2 14-bit PWM (DA output) The 14-bit PWM automatically outputs a PWM rectangular waveform from the D-A pin by writing high-order 8 bits of the output data to the DA-H register and the low-order 6 bits to the DA-L register. Data of the DA-H register are transferred to the 14-bit PWM circuit when writing to the DA-L register.

  • Page 93: Fig. 2.10.3 14-Bit Pwm Output Example

    FUNCTIONAL DESCRIPTION 2.10 PWM Set “28 ” to DA-L register. Set “2C ” to DA-H register. b6 b5 b4 b3 b2 b1 b6 b5 b4 b3 b2 b1 [DA-H [DA-L register] register] Undefined At writing of DA-L At writing of DA-L [DA latch] These bits decide HIGH level area These bits decide smaller interval “tm”...

  • Page 94: 8-Bit Pwm (Pwm0 To Pwm5: Address 00D0 To 00D4 And 00F6 )

    FUNCTIONAL DESCRIPTION 2.10 PWM 2.10.3 8-bit PWM (PWM0 to PWM5: address 00D0 to 00D4 and 00F6 The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to bits 0 to 7 of the 8-bit PWM register. That is to say, 8 kinds of pulses corresponding to the weight of each bit of the 8-bit PWM register are output inside the circuit during 1 cycle.
  • Page 95 FUNCTIONAL DESCRIPTION 2.10 PWM Fig. 2.10.4 Pulse waveforms corresponding to weight Fig. 2.10.5 Example of 8-bit PWM output of each bit of 8-bit PWM register 7220 Group User’s Manual 2-68...

  • Page 96: 14-Bit Pwm Output Control

    FUNCTIONAL DESCRIPTION 2.10 PWM 2.10.4 14-bit PWM output control How to control the 14-bit PWM output is described below. Set “0” to bit 0 of PWM output control register 1 (address 00D5 ) to supply the PWM count source (this bit is cleared to “0”...

  • Page 97: 8-Bit Pwm Output Control

    FUNCTIONAL DESCRIPTION 2.10 PWM 2.10.5 8-bit PWM output control How to control the 8-bit PWM output is described below. The PWM0–PWM7 output pins are also used for port P0 –P0 and P6 –P6 Set “0” to bit 0 of the PWM output control register 1 (address 00D5 ) to supply the PWM count source (this bit is cleared to “0”...

  • Page 98: Crt Display Function

    FUNCTIONAL DESCRIPTION 2.11 CRT display function 2.11 CRT display function Table 2.11.1 shows the outline the CRT display function of the M37221M6-XXXSP/FP. M37220M3-XXXSP/FP Refer to “CHAPTER 4. M37220M3-XXXSP/FP.” The M37221M6-XXXSP/FP has the 24 characters 2 lines CRT display circuit. CRT display is controlled by the CRT control register.

  • Page 99: Fig. 2.11.2 Crt Display Circuit Block Diagram

    FUNCTIONAL DESCRIPTION 2.11 CRT display function OSC1 OSC2 SYNC SYNC (Address 00EA CRT control register Display oscillation circuit (Addresses 00E1 , 00E2 Vertical position registers (Address 00E4 Character size register Display position control circuit (Address 00E0 Horizontal position register (Address 00E5 Border selection register Display control circuit...

  • Page 100: Fig. 2.11.3 Crt Control Register (Address 00Ea 16 )

    FUNCTIONAL DESCRIPTION 2.11 CRT display function CRT Control Register b7 b6 b5 b4 b3 b2 b1 b0 CRT control register (CC) [Address 00EA Functions After reset R W Name 0 : All-blocks display off All-blocks display control 1 : All-blocks display on bit (Note) (CC0) 0 : Block 1 display off Block 1 display control bit...

  • Page 101: Display Position

    FUNCTIONAL DESCRIPTION 2.11 CRT display function 2.11.1 Display position The display positions of characters are specified in units called a “block”. There are 2 blocks, block 1 and block 2. Up to 24 characters can be displayed in 1 block (refer to “2.11.3 Memory for display”). The display position of each block in both horizontal and vertical directions can be set by software.

  • Page 102: Fig. 2.11.5 Display Position

    FUNCTIONAL DESCRIPTION 2.11 CRT display function The block 2 is displayed after the display of block 1 is completed (refer to “Figure 2.11.5 (a)”). Therefore, set vertical display start position of block 2 to be lower than the display end position of block 1. The block 2 cannot display when the display position of block 2 is overlapped with the display position of block 1 (refer to “Figure 2.11.5 (b)”) or is higher than the display position of block 1 (refer to “Figure 2.11.5 (c)”).

  • Page 103: Fig. 2.11.6 Vertical Position Register N

    FUNCTIONAL DESCRIPTION 2.11 CRT display function The vertical position can specify 128-step positions (4 scanning lines per step) for each block by setting values “00 ” to “7F ” to bits 0 to 6 of the vertical position registers (the blocks 1 and 2 are assigned to addresses to 00E1 , 00E2 respectively).

  • Page 104: Character Size

    FUNCTIONAL DESCRIPTION 2.11 CRT display function 2.11.2 Character size The size of characters to be displayed can select from 3 sizes for each block. Set a character size by the character size register (address 00E4 The character size in block 1 can be specified by bits 0 and 1 of the character size register; the character size in block 2 can be specified by bits 2 and 3.

  • Page 105: Memory For Display

    FUNCTIONAL DESCRIPTION 2.11 CRT display function 2.11.3 Memory for display There are 2 types of display memory: CRT display ROM (addresses 10000 to 11FFF ) used to store (masked) character dot data and CRT display RAM (addresses 0600 to 06B7 ) used to specify the colors and characters to be displayed.

  • Page 106: Table 2.11.3 Character Code Table (Be Omitted Partly)

    FUNCTIONAL DESCRIPTION 2.11 CRT display function The character code used to specify a display character is determined based on the address in the CRT display ROM in which that character data is stored. Assume that 1 character data is stored in addresses 10XX0 to 10XXF (XX denotes “00 ”...

  • Page 107: Table 2.11.4 Contents Of Crt Display Ram

    FUNCTIONAL DESCRIPTION 2.11 CRT display function (2) CRT display RAM (addresses 0600 to 06B7 CRT display RAM is assigned to addresses 0600 to 06B7 , and is divided into a display character code specification part and display color specification part for each block. Table 2.11.4 shows the contents of CRT display RAM.

  • Page 108: Fig. 2.11.11 Structure Of Crt Display Ram

    FUNCTIONAL DESCRIPTION 2.11 CRT display function Figure 2.11.11 shows the structure of CRT display RAM. Block 1 [Character specification] 1st character : 0600 24th character : 0617 Character code Specify 256 characters (“00 ” to “FF ”) [Color specification] 1st character : 0680 24th character : 0697 Color register specification 0 0 : Specifying color register 0...

  • Page 109: Fig. 2.11.12 Color Register N

    FUNCTIONAL DESCRIPTION 2.11 CRT display function 2.11.4 Color registers A display character color can be specified by setting a color to one of 4 color registers (CO0 to CO3: addresses 00E6 to 00E9 ) and then by specifying the color register with the CRT display RAM. There are 3 color outputs: R, G, and B.

  • Page 110: Color Registers

    FUNCTIONAL DESCRIPTION 2.11 CRT display function Table 2.11.5 Display example of character background coloring (when green is set for a character and blue is set for background color) Border selection register Color register G output B output OUT1 output Character output OUT2 output Green No output...

  • Page 111: Multiline Display

    FUNCTIONAL DESCRIPTION 2.11 CRT display function 2.11.5 Multi-line display The M37221M6-XXXSP/FP can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addition, it can display up to 16 lines by using a CRT interrupt. A CRT interrupt request occurs at which display of each block has been completed.

  • Page 112: Character Border Function

    FUNCTIONAL DESCRIPTION 2.11 CRT display function 2.11.6 Character border function An border of 1 clock (1 dot) equivalent size can be added to a display character in both horizontal and vertical directions. The border is output from pin Character data dots OUT 1.

  • Page 113: Crt Output Pin Control

    FUNCTIONAL DESCRIPTION 2.11 CRT display function 2.11.7 CRT output pin control CRT display output pins R, G, B, and OUT1 are also used for ports P5 –P5 respectively. When clearing the corresponding bits of the port P5 direction register (address 00CB ) to “0,”...

  • Page 114: Raster Coloring Function

    FUNCTIONAL DESCRIPTION 2.11 CRT display function 2.11.8 Raster coloring function R, G, B, and OUT1 output can be switched to MUTE output. MUTE output can color all displaying area (raster) of screen. For example, the case that pin B is specified for MUTE signal output is shown in Figure 2.11.18. When the MUTE signal is output from pin B, the background of the entire screen is colored “BLUE.”...

  • Page 115: Clock For Display

    FUNCTIONAL DESCRIPTION 2.11 CRT display function 2.11.9 Clock for display As a clock for display to be used for CRT display, it is possible to select one of the following 4 types. Main clock supplied from the X Main clock supplied from the X pin divided by 1.5 Clock from the LC or RC supplied from the pins OSC1 and OSC2.

  • Page 116: Rom Correction Function

    FUNCTIONAL DESCRIPTION 2.12 ROM correction function 2.12 ROM correction function Only the M37221M8-XXXSP and the M37221MA-XXXSP have this function. This can correct ROM program data in ROM. Up to 2 addresses (2 blocks) can be corrected, a program for correction is stored in the ROM correction memory in RAM. The ROM memory for correction is 32 bytes 2 blocks.

  • Page 117: Software Runaway Detect Function

    FUNCTIONAL DESCRIPTION 2.13 Software runaway detect function 2.13 Software runaway detect function The M37221M6-XXXSP/FP has a function to decode undefined instructions to detect a software runaway. When an undefined op-code is input to the CPU as an instruction code during operation of the M37221M6- XXXSP/FP, the following processing is done.

  • Page 118: Low-Power Dissipation Mode

    FUNCTIONAL DESCRIPTION 2.14 Low-power dissipation mode 2.14 Low-power dissipation mode The M37221M6-XXXSP/FP has 2 low-power dissipation modes: the stop mode and the wait mode. 2.14.1 Stop mode The M37221M6-XXXSP/FP allows the oscillation of X to be stopped with keeping all states of registers except timers 3 and 4, input/output ports, and internal RAM.

  • Page 119: Fig. 2.14.1 Oscillation Stabilizing Time At Return By Reset Input

    FUNCTIONAL DESCRIPTION 2.14 Low-power dissipation mode Time to hold internal reset state = approximately 32768 cycles of X input Stop mode Oscillation stabilizing time 2 µ s or more RESET (Note) Execute STP instruction Returned by reset input Fig. 2.14.1 Oscillation stabilizing time at return by reset input lWhen returning from stop mode by using INT1 interrupt (rising edge selected) Oscillation stabilizing time Stop mode...

  • Page 120: Wait Mode

    FUNCTIONAL DESCRIPTION 2.14 Low-power dissipation mode 2.14.2 Wait mode The wait mode is set by executing the WIT instruction. In the wait mode, only the internal clock φ stops with supplying f(X ) continuously. In this case, there is no need to create a wait time by timers as in the case of return from the stop mode, and operation is restarted immediately after return from the wait state.

  • Page 121: Reset

    FUNCTIONAL DESCRIPTION 2.14 Low-power dissipation mode Reset Wait mode Ordinary mode Stop mode 8 MHz oscillating 8 MHz oscillating φ 8 MHz stopped is stopped φ φ = 4 MHz is stopped Timer operating (Note 2) (Note 1) = 8 MH * at f(X Notes 1: The following interrupts are invalid in the wait mode.

  • Page 122: Reset Operation

    FUNCTIONAL DESCRIPTION 2.15 Reset 2.15 Reset To reset the microcomputer, applied LOW level to pin RESET for 2 µ s or more. Reset is released when HIGH level is applied to pin RESET, and the program starts from the address indicated with the reset vector table.

  • Page 123: Internal State Immediately After Reset

    FUNCTIONAL DESCRIPTION 2.15 Reset 2.15.2 Internal state immediately after reset Figures 2.15.2 to 2.15.4 show the internal state immediately after reset. SFR Area (addresses C0 to DF State immediately after reset < > : “0” immediately after reset : “1” immediately after reset : Indeterminate immediately after reset Register...

  • Page 124: Fig. 6.7.28 Interrupt Request Register 1

    FUNCTIONAL DESCRIPTION 2.15 Reset SFR Area (addresses E0 to FF State immediately after reset < > : “0” immediately after reset : “1” immediately after reset : Indeterminate immediately after reset Register State immediately after reset Address Horizontal position register (HR) Vertical position register 1 (CV1) Vertical position register 2 (CV2) Character size register (CS)
  • Page 125 FUNCTIONAL DESCRIPTION 2.15 Reset 2 Page Register Area (addresses 217 to 21B State immediately after reset < > : “0” immediately after reset : “1” immediately after reset : Indeterminate immediately after reset Register State immediately after reset Address ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order)

  • Page 126: Notes For Poweron Reset

    FUNCTIONAL DESCRIPTION 2.15 Reset 2.15.3 Notes for poweron reset When poweron reset, set the external reset circuit Power source so that the reset input voltage must be kept 0.6 V voltage M37221M6- or less until the power source voltage reaches 4.5 V XXXSP/FP 4.5 V after the power is turned on.

  • Page 127: Clock Generating Circuit

    FUNCTIONAL DESCRIPTION 2.16 Clock generating circuit 2.16 Clock generating circuit Oscillation circuit consists of an “oscillation gate” which operates as an amplifier to provide the gain required for oscillation and an “oscillating control flip-flop” to control this. Because of that, it is possible to start and stop oscillating as required.

  • Page 128: Oscillation Circuit

    FUNCTIONAL DESCRIPTION 2.17 Oscillation circuit 2.17 Oscillation circuit The M37221M6-XXXSP/FP has a internal oscillation circuits used to obtain the clocks required for operation. divided by 2 is the internal clock (internal timing output) φ . Ordinarily, the frequency on clock input pin X A quartz-crystal oscillator or ceramic resonator can be connected externally to these circuits.

  • Page 129: Chapter 3. Electrical Characteristics

    C H A P T E R 3 ELECTRICAL CHARACTERISTICS 3.1 Electrical characteristics 3.2 Standard characteristics...
  • Page 130 ELECTRICAL CHARACTERISTICS 3.1 Electrical characteristics 3.1 Electrical characteristics Absolute maximum ratings Parameter Symbol Conditions Ratings Unit Power source voltage V All voltages are –0.3 to 6 Input voltage based on V –0.3 to 6 Input voltage –P0 –P1 , P2 –...
  • Page 131 ELECTRICAL CHARACTERISTICS 3.1 Electrical characteristics Recommended operating conditions (T = –10 °C to 70 °C, V = 5 V ± 10 %, unless otherwise noted) Parameter Min. Typ. Max. Symbol Unit Power source voltage (Note 4), During CPU, CRT operation Power source voltage HIGH input voltage –P0...
  • Page 132 ELECTRICAL CHARACTERISTICS 3.1 Electrical characteristics Electric characteristics (V = 5 V ± 10 %, V = 0 V, f(X ) = 8 MHz, T = –10 °C to 70 °C, unless otherwise noted) Limits Symbol Test conditions Unit Parameter Typ. Max.

  • Page 133: Fig. 3.1.1 Definition Diagram Of Timing On Multi-Master I

    ELECTRICAL CHARACTERISTICS 3.1 Electrical characteristics A-D Comparator characteristics = 5 V ± 10 %, V = 0 V, f(X ) = 8 MHz, T = –10 °C to 70 °C, unless otherwise noted) Limits Unit Test conditions Parameter Symbol Min. Typ.
  • Page 134 ELECTRICAL CHARACTERISTICS 3.1 Electrical characteristics 3.2 Standard characteristics 3.2 Standard characteristics The data described in this section are characteristic examples. Refer to “3.1 Electrical characteristics” for rated values. 1. Ports P0 –P0 and P3 –V characteristics 100.00 80.00 =5.5V 60.00 40.00 =4.5V 20.00...
  • Page 135 ELECTRICAL CHARACTERISTICS 3.1 Electrical characteristics 3.2 Standard characteristics 3. Ports P1 , P1 –P1 , P2 –P2 , P3 and D-A –V characteristics 100.00 80.00 60.00 =5.5V 40.00 =4.5V 20.00 0.000 0.000 1.200 2.400 3.600 4.800 6.000 LOW level output voltage V characteristics OH–...
  • Page 136 ELECTRICAL CHARACTERISTICS 3.1 Electrical characteristics 3.2 Standard characteristics 4. Ports P1 –P1 characteristics OL– 100.00 80.00 =5.5V 60.00 =4.5V 40.00 20.00 0.000 0.000 1.200 2.400 3.600 4.800 6.000 LOW level output voltage V –V characteristics – 100.00 – 80.00 – 60.00 =5.5V –...
  • Page 137 ELECTRICAL CHARACTERISTICS 3.1 Electrical characteristics 3.2 Standard characteristics 5. Ports P2 –P2 characteristics OL– 100.00 80.00 60.00 =5.5V 40.00 =4.5V 20.00 0.000 0.000 1.200 2.400 3.600 4.800 6.000 LOW level output voltage V –V characteristics – 100.00 – 80.00 – 60.00 =5.5V –...
  • Page 138 ELECTRICAL CHARACTERISTICS 3.1 Electrical characteristics 3.2 Standard characteristics 6. Ports P5 –P5 characteristics OL– 100.00 80.00 60.00 40.00 =5.5V 20.00 =4.5V 0.000 0.000 1.200 2.400 3.600 4.800 6.000 LOW level output voltage V –V characteristics – 100.00 – 80.00 – 60.00 –...

  • Page 139: Chapter 4. M37220M3-Xxxsp/Fp

    C H A P T E R 4 M37220M3-XXXSP/FP 4.1 Performance overview 4.2 Pin configuration 4.3 Pin description 4.4 Functional block diagram 4.5 Functional description 4.6 Electrical characteristics 4.7 Standard characteristics...

  • Page 140: Table 4.1.1 Performance Overview (1)

    M37220M3-XXXSP/FP 4.1 Performance overview 4.1 Performance overview This chapter is described about M37220M3-XXXSP/FP. M37220M3-XXXSP/FP has the common functions with M37221M6-XXXSP/FP except for part of functions. This chapter explains the differences between M37220M3-XXXSP/FP and M37221M6-XXXSP/FP. Therefore, refer to the corresponding descriptions of M37221M6-XXXSP/FP about the common functions. The 8-bit microcomputer M37220M3-XXXSP/FP has many additional functions for tuning system for TV: Table 4.1.1 Performance overview (1) Parameter...
  • Page 141 M37220M3-XXXSP/FP 4.1 Performance overview Table 4.1.2 Performance overview (2) Parameter Performance Power dissipation CRT ON 165 mW typ. (at oscillation frequency f(X ) = 8 MHz, = 8 MHz) CRT OFF 110 mW typ. (at oscillation frequency f(X ) = 8 MHz) In stop mode 1.65 mW (maximum) 12V withstand ports...

  • Page 142: Fig. 4.2.1 Pin Configuration (Top View) (1)

    M37220M3-XXXSP/FP 4.2 Pin configuration 4.2 Pin configuration The pin configurations are shown in Figures 4.2.1 and 4.2.2. SYNC SYNC /PWM0 /PWM1 /OUT /PWM2 /PWM3 /PWM4 /PWM5 /INT2/A-D4 /INT1 /TIM3 /TIM2 /A-D1/INT3 /A-D2 /A-D3 /A-D5/DA1 /A-D6/DA2 RESET OSC1/P3 OSC2/P3 Package type : 42P4B Fig.

  • Page 143: Fig. 4.2.2 Pin Configuration (Top View) (2)

    M37220M3-XXXSP/FP 4.2 Pin configuration SYNC SYNC /PWM0 /PWM1 /OUT /PWM2 /PWM3 /PWM4 /PWM5 /INT2/A-D4 /INT1 /TIM3 /TIM2 /A-D1/INT3 /A-D2 /A-D3 /A-D5/DA1 /A-D6/DA2 RESET OSC1/P3 OSC2/P3 Package type : 42P2R-A Fig. 4.2.2 Pin configuration (top view) (2) 7220 Group User’s Manual...

  • Page 144: Table 4.3.1 Pin Description (1)

    M37220M3-XXXSP/FP 4.3 Pin description 4.3 Pin description The pin description of M37220M3-XXXSP/FP is shown in Table 4.3.1. Table 4.3.1 Pin description (1) Input/ Name Functions Output Power source Apply voltage of 5 V ± 10 % (typical) to V , and 0 V to V This is connected to V RESET Reset input...

  • Page 145: Table 4.3.2 Pin Description (2)

    M37220M3-XXXSP/FP 4.3 Pin description Table 4.3.2 Pin description (2) Input/ Name Functions Output I/O port P2 Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. External clock Input Pins P2 , P2...
  • Page 146 M37220M3-XXXSP/FP 4.4 Functional block diagram 4.4 Functional block diagram The functional block diagram is shown in Figure 4.4.1. 7220 Group User’s Manual...

  • Page 147: Table 4.5.1 Difference Between M37220M3-Xxxsp/Fp And M37221M6-Xxxsp/Fp

    M37220M3-XXXSP/FP 4.5 Functional description 4.5 Functional description Functions of M37220M3-XXXSP/FP are partially different from those of M37221M6-XXXSP/FP. Table 4.5.1 shows the difference between M37220M3-XXXSP/FP and M37221M6-XXXSP/FP. Table 4.5.1 Difference between M37220M3-XXXSP/FP and M37221M6-XXXSP/FP M37221M6-XXXSP/FP Paramater M37220M3-XXXSP/FP Programmable I/O ports 8 bits Port P0 8 bits 8 bits...

  • Page 148: Access Area

    M37220M3-XXXSP/FP 4.5 Functional description 4.5.1 Access area Figure 4.5.1 shows the M37220M3-XXXSP/FP access area. 0000 10000 65536 Internal RAM CRT display ROM (192 bytes) (4 K bytes) Zero page for display 00C0 SFR area Special function register 10FFF 69631 (256 bytes) (Refer to Figures 4.5.3 and 4.5.4) 00FF Internal RAM...

  • Page 149: Memory Assignment

    M37220M3-XXXSP/FP 4.5 Functional description 4.5.2 Memory assignment Figure 4.5.2 shows the memory assignment M37220M3-XXXSP/FP. Hexadecimal notation Decimal notation 0000 10000 65536 Internal RAM CRT display ROM (192 bytes) (4 K bytes) for display 00C0 SFR area Zero page Special function register 10FFF 69631 (256 bytes)

  • Page 150: Fig. 4.5.3 Memory Map Of Sfr (Special Function Register) (1)

    M37220M3-XXXSP/FP 4.5 Functional description SFR Area (addresses C0 to DF Bit allocation < > State immediately after reset < > : “0” immediately after reset Function bit : “1” immediately after reset Name No function bit : Undefined immediately after reset : Fix this bit to “0”...

  • Page 151: Fig. 4.5.4 Memory Map Of Sfr (Special Function Register) (2)

    M37220M3-XXXSP/FP 4.5 Functional description SFR Area (addresses E0 to FF Bit allocation State immediately after reset < > < > : “0” immediately after reset Function bit : “1” immediately after reset Name No function bit : Undefined immediately after reset : Fix this bit to “0”...

  • Page 152: Input/Output Pins

    M37220M3-XXXSP/FP 4.5 Functional description 4.5.3 Input/Output pins Table 4.5.2 shows the difference of programmable ports between M37221M6-XXXSP/FP and M37220M3- XXXSP/FP. Table 4.5.2 Difference of programmable ports between M37221M6-XXXSP/FP and M37220M3- XXXSP/FP Functions except port Port M37221M6-XXXSP/FP M37220M3-XXXSP/FP –P0 PWM0–PWM5 INT2/A-D4 INT1 OUT2 No function...

  • Page 153: Interrupts

    M37220M3-XXXSP/FP 4.5 Functional description 4.5.4 Interrupts The M37220M3-XXXSP/FP has 13 sources (reset is included) of interrupts. Table 4.5.3 Interrupt sources, vector addresses and priority Vector addresses Interrupt sources Remarks Priority High-order byte Low-order byte Reset (Note) FFFF FFFE Non-maskable CRT interrupt FFFD FFFC INT2 interrupt...

  • Page 154: Fig. 4.5.5 Interrupt Request Register

    M37220M3-XXXSP/FP 4.5 Functional description Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC Name Functions After reset R W 0 : No interrupt request issued Timer 1 interrupt 1 : Interrupt request issued request bit (TM1R) 1 Timer 2 interrupt...

  • Page 155: D-A Converter

    M37220M3-XXXSP/FP 4.5 Functional description 4.5.5 D-A converter M37220M3-XXXSP/FP has 2 D-A converter with 6-bit resolution. Figure 4.5.7 shows the D-A converter block diagram. Data bus DA1 conversion register DA2 conversion register (address 00DE (address 00DF Resistor ladder Resistor ladder DA1 output enable bit DA2 output enable bit /A-D5/DA1 /A-D6/DA2...

  • Page 156: Fig. 4.5.8 Da N Conversion Register

    M37220M3-XXXSP/FP 4.5 Functional description DA n Conversion Register b7 b6 b5 b4 b3 b2 b1 b0 DA n conversion register (DAn) (n = 1 and 2) [Address 00DE , 00DF Name Functions After reset DA conversion set Indeterminate : 0/64Vcc bits : 1/64Vcc (DAn0–DAn5)

  • Page 157: Crt Display Function

    M37220M3-XXXSP/FP 4.5 Functional description 4.5.6 CRT Display function Table 4.5.5 shows the outline the CRT display function of the M37220M3-XXXSP/FP. Table 4.5.5 Outline of CRT display function Parameter Performance Number of display character 20 characters 2 lines Dot structure 12 dots 16 dots Kinds of character 128 kinds...

  • Page 158: Fig. 4.5.10 Crt Display Circuit Block Diagram

    M37220M3-XXXSP/FP 4.5 Functional description OSC1 OSC2 SYNC SYNC (Address 00EA CRT control register Display oscillation circuit (Addresses 00E1 , 00E2 Vertical position registers (Address 00E4 Character size register Display position control circuit (Address 00E0 Horizontal position register (Address 00E5 Border selection register Display control circuit RAM for display...

  • Page 159: Fig. 4.5.11 Example Of Display Character Data Storing Form

    M37220M3-XXXSP/FP 4.5 Functional description (1) Memory for display There are 2 types of display memory: CRT display ROM (addresses 10000 to 10FFF ) and CRT display RAM (addresses 0600 to 06B3 ). Each type of display memory is described below. CRT display ROM (addresses 10000 to 10FFF CRT display ROM has a capacity of 4 K bytes.

  • Page 160: Table 4.5.6 Character Code Table (Be Omitted Partly)

    M37220M3-XXXSP/FP 4.5 Functional description The character code used to specify a display character is determined based on the address in the CRT display ROM in which that character data is stored. Assume that 1 character data is stored in addresses 10XX0 to 10XXF (XX denotes 00 to 7F...

  • Page 161: Fig. 4.5.12 Structure Of Crt Display Ram

    M37220M3-XXXSP/FP 4.5 Functional description Figure 4.5.12 shows the structure of CRT display RAM. Block 1 [Character specification] 1st character : 0600 20th character : 0613 Character code Specify 128 characters (“00 ” to “7F ”) [Color specification] 1st character : 0680 20th character : 0693 Color register specification 0 0 : Specifying color register 0...

  • Page 162: Fig. 4.5.13 Border Selection Register

    M37220M3-XXXSP/FP 4.5 Functional description The different CRT display function–related registers from those of M37221M6-XXXSP/FP are shown in the following pages. Border Selection Register b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E5 Name Functions After reset Block 1 OUT output 0 : Same output as character output Indeterminate...

  • Page 163: Fig. 4.5.15 Crt Control Register

    M37220M3-XXXSP/FP 4.5 Functional description CRT Control Register b7 b6 b5 b4 b3 b2 b1 b0 CRT control register (CC) [Address 00EA Name Functions After reset R W All-blocks display control 0 : All-blocks display off bit (Note) (CC0) 1 : All-blocks display on Block 1 display control bit 0 : Block 1 display off (CC1)

  • Page 164: Internal State Immediately After Reset

    M37220M3-XXXSP/FP 4.5 Functional description 4.5.7 Internal state immediately after reset Figures 4.5.17 and 4.5.18 show the internal state immediately after reset. SFR Area (addresses C0 to DF State immediately after reset < > : “0” immediately after reset : “1” immediately after reset : Undefined immediately after reset Register...
  • Page 165 M37220M3-XXXSP/FP 4.5 Functional description SFR Area (addresses E0 to FF State immediately after reset < > : “0” immediately after reset : “1” immediately after reset : Undefined immediately after reset Register State immediately after reset Address Horizontal position register (HR) Vertical position register 1 (CV1) Vertical position register 2 (CV2) Character size register (CS)

  • Page 166: Electrical Characteristics

    M37220M3-XXXSP/FP 4.6 Electrical characteristics 4.6 Electrical characteristics Absolute maximum ratings Symbol Ratings Parameter Conditions Unit Power source voltage V –0.3 to 6 All voltages are Input voltage –0.3 to 6 based on V Input voltage –P0 –P1 , P2 – –0.3 to V + 0.3 Output transistors...
  • Page 167 M37220M3-XXXSP/FP 4.6 Electrical characteristics Recommended operating conditions (T = –10 °C to 70 °C, V = 5 V ± 10 %, unless otherwise noted) Parameter Min. Typ. Max. Symbol Unit Power source voltage (Note 4), During CPU, CRT operation Power source voltage 0.8V HIGH input voltage –P0...
  • Page 168 M37220M3-XXXSP/FP 4.6 Electrical characteristics Electric characteristics (V = 5 V ± 10 %, V = 0 V, f(X ) = 8 MHz, T = –10 °C to 70 °C, unless otherwise noted) Limits Unit Symbol Test conditions Parameter Typ. Max. Min.
  • Page 169 M37220M3-XXXSP/FP 4.6 Electrical characteristics A-D Comparator characteristics = 5 V ± 10 %, V = 0 V, f(X ) = 8 MHz, T = –10 °C to 70 °C, unless otherwise noted) Limits Unit Test conditions Parameter Symbol Min. Typ. Max.

  • Page 170: Standard Characteristics

    M37220M3-XXXSP/FP 4.7 Standard characteristics 4.7 Standard characteristics The data described in this section are characteristic examples. Refer to “4.6 Electrical characteristics” for rated values. 1. Ports P0 –P0 and P3 –V characteristics 100.00 80.00 =5.5V 60.00 40.00 =4.5V 20.00 0.000 0.000 1.200 2.400...
  • Page 171 M37220M3-XXXSP/FP 4.7 Standard characteristics 3. Ports P1 –P1 , P2 –P2 , P3 and D-A –V characteristics 100.00 80.00 60.00 =5.5V 40.00 =4.5V 20.00 0.000 0.000 1.200 2.400 3.600 4.800 6.000 LOW level output voltage V characteristics OH– – 100.00 –...
  • Page 172 M37220M3-XXXSP/FP 4.7 Standard characteristics 4. Ports P2 –P2 characteristics OL– 100.00 80.00 60.00 =5.5V 40.00 =4.5V 20.00 0.000 0.000 1.200 2.400 3.600 4.800 6.000 LOW level output voltage V –V characteristics – 100.00 – 80.00 – 60.00 =5.5V – 40.00 –...
  • Page 173 M37220M3-XXXSP/FP 4.7 Standard characteristics 5. Ports P5 –P5 characteristics OL– 100.00 80.00 60.00 40.00 =5.5V 20.00 =4.5V 0.000 0.000 1.200 2.400 3.600 4.800 6.000 LOW level output voltage V –V characteristics – 100.00 – 80.00 – 60.00 – 40.00 – 20.00 =5.5V =4.5V...

  • Page 174: Chapter 5. Application

    C H A P T E R 5 APPLICATION 5.1 Example of multi-line display 5.2 Notes on programming for OSD (M37220M3-XXXSP/FP) 5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP) 5.4 Example of I C-BUS interface control (M37221Mx-XXXSP/FP) 5.5 Example of I C-BUS interface control by software (M37220M3-XXXSP/FP) 5.6 Application circuit example...

  • Page 175: Specifications

    APPLICATION 5.1 Example of multi-line display 5.1 Example of multi-line display The M37221Mx-XXXSP/FP is used as a general example in describing this application for the 7220 group. The M377221Mx-XXXSP/FP ordinarily displays 2 lines on a CRT screen by displaying 2 blocks at different vertical positions.

  • Page 176: General Flowchart

    APPLICATION 5.1 Example of multi-line display 5.1.3 General flowchart The multi-line display processing routine consists of initialization processing routine, V interrupt processing SYNC routine, and CRT interrupt processing routine. (1) Initialization processing routine This routine is used to initialize to cause a CRT interrupt. CRTE : Bit 4 of interrupt control register 1 Line counter :...

  • Page 177: Fig. 5.1.4 Flowchart Of V

    APPLICATION 5.1 Example of multi-line display (2) V interrupt processing routine SYNC The V interrupt processing routine consists of; multi-line display start processing and multi-line SYNC display correction processing. The correction processing corrects erroneous multi-line display due to various influences. ICON1, ICON2: Interrupt control registers 1, 2 CC :...

  • Page 178: Fig. 5.1.5 Flowchart Of Crt Interrupt Processing Routine

    APPLICATION 5.1 Example of multi-line display (3) CRT interrupt processing routine The CRT interrupt processing routine executes the display character data setup routine for each line, in order to perform multi-line display. The line to be displayed is determined by the line counter value. ICON1, ICON2: Interrupt control registers 1, 2 CS :...

  • Page 179: Fig. 5.1.6 Set Of Display Character Data

    APPLICATION 5.1 Example of multi-line display 5.1.4 Set of display character data To display the character data, set the character codes (“00 ” to “FF ”) in the character addresses (block 1: addresses 0600 to 0617 , block 2: addresses 0620 to 0637 ).

  • Page 180: Fig. 5.1.7 Example Of Setup Timing For Line Counter And Display Character Data

    APPLICATION 5.1 Example of multi-line display 5.1.5 Line counter The line counter determines which line of display data is to be set. For example, if a CRT interrupt occurs at the end of the first line display, the line counter value will be “2.” Therefore, the 3rd line display data must be set from the end of the 1st line display to the start of the 3rd line display.

  • Page 181: Processing Time

    APPLICATION 5.1 Example of multi-line display 5.1.6 Processing time When setting display data by a CRT interrupt, the processing time is limited. As shown in Figure 5.1.7, a CRT interrupt occurs at the end of the first line (block 1) display and setting for the 3rd line display is started.

  • Page 182: Set Of Multiple Interrupts

    APPLICATION 5.1 Example of multi-line display 5.1.7 Set of multiple interrupts (1) When not setting multiple interrupts When two or more interrupt requests occur at the same sampling point, the interrupt with the higher priority (refer to “2.5 Interrupts, Table 2.5.1”) is received. This priority level is determined by hardware but various priority processing by software can be executed using the interrupt enable bit and each interrupt disable flag (I).

  • Page 183: Fig. 5.1.9 Timing When All Interrupt Request Bits Are "1" At The Same Sampling Point

    APPLICATION 5.1 Example of multi-line display (2) When setting multiple interrupts Various priority processings are executed by enabling multiple interrupts and by setting priorities by software. For example, to set the priority listed below; Timer 1 interrupt interrupt SYNC CRT interrupt execute the following process: Set only interrupt enable bits (ICON1, ICON2) whose priorities are higher than the current interrupt, and enable the interrupt disable flag (I) in only the current interrupt processing routine.

  • Page 184: Fig. 5.1.10 Flowchart Of Crt Interrupt Processing Routine (When Setting Multiple Interrupts)

    APPLICATION 5.1 Example of multi-line display (3) CRT interrupt processing routine when setting multiple interrupts Figure 5.1.10 shows the flowchart of CRT interrupt processing routine when setting multiple interrupts. A and B are the setting routines for multiple interrupts. ICON1, ICON2: Interrupt control registers 1, 2 CRT_ICON1, CRT_ICON2 : Back up RAM for interrupt control...

  • Page 185: Fig. 5.1.11 Flowchart Of V

    APPLICATION 5.1 Example of multi-line display (4) V interrupt processing routine when setting multiple interrupts SYNC Figure 5.1.11 shows the flowchart of V interrupt processing routine when setting multiple interrupts. SYNC A’ and B’ are the setting routines for multiple interrupts. ICON1, ICON2: Interrupt control registers 1, 2 V_ICON1, V_ICON2 :...

  • Page 186: Notes On Programming For Osd (M37220M3-Xxxsp/Fp)

    APPLICATION 5.2 Notes on programming for OSD (M37220M3-XXXSP/FP) 5.2 Notes on programming for OSD (M37220M3-XXXSP/FP) The emulator MCU M37221ERSS is used for programming development with the M37220M3-XXXSP/FP. However, the functions of the M37221ERSS are compatible with those of the M37221Mx-XXXSP/FP, and therefore has some functions which the M37220M3-XXXSP/FP does not have.

  • Page 187: Setting Of Border Selection Register

    APPLICATION 5.2 Notes on programming for OSD (M37220M3-XXXSP/FP) Color Register n b7 b6 b5 b4 b3 b2 b1 b0 Color register n (COn) (n = 0 to 3) [Addresses 00E6 to 00E9 Name Functions After reset R W Nothing is assigned. This bit is a write disable bit. R —...

  • Page 188: Usage Example Of Rom Correction Function (M37221M8/Ma-Xxxsp)

    APPLICATION 5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP) 5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP) Application example using the ROM correction function is described below. In this example, it is assumed that the program must be changed by specifications modification after completion of ROM mask. Also, PROM is connected to this system.

  • Page 189: Fig. 5.3.3 Correction Example (2)

    APPLICATION 5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP) (2) Correction example 2 The loop processing is performed between in Figure 5.3.3. Two examples of this part are shown in detail. Example A corrects in loop units and example B corrects only error instructions. Examples A and B are the same operation, differing in processing time and correction bytes only.

  • Page 190: E 2 Prom Map

    APPLICATION 5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP) 5.3.3 E PROM map Figures 5.3.4 and 5.3.5 show the E PROM map when using the ROM correction function. To store correction codes by using both ROM correction functions 1 and 2, the capacity of E PROM needs to be approximately 70 bytes.

  • Page 191: Fig. 5.3.5 E 2 Prom Map When Using Rom Correction Function (2)

    APPLICATION 5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP) Contents Stored data Instructions in PROM (Machine instruction) correction program address Valid/invalid ROM correction function 2 (55H: valid, others: invalid) ROM correction function 2 Execution address (high-order) ROM correction function 2 Execution address (low-order) 025H, X ROM correction function 2...

  • Page 192: General Flowchart

    APPLICATION 5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP) 5.3.4 General flowchart Figure 5.3.6 shows the general flowchart when using ROM correction function. E PROM addresses in the flowchart corresponds to E PROM map (refer to “Figures 5.3.4 and 5.3.5”). START After reset release, read the data from E...

  • Page 193: Notes On Use

    APPLICATION 5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP) 5.3.5 Notes on use When using the ROM correction function, note the following. Specify the first address (op code address) of each instruction as the ROM correction address. Use the RTS, RTI or JMP instruction (total of 3 bytes) to return from the correction program to the main program.

  • Page 194: Example Of I

    APPLICATION 5.4 Example of I C-BUS interface control (M37221Mx-XXXSP/FP) 5.4 Example of I C-BUS interface control (M37221Mx-XXXSP/FP) The M37221Mx-XXXSP/FP has multi-master I C-BUS interface. This interface, offering both arbitration lost detection and synchronous functions, is useful for the multi-master serial communications. This paragraph explains transmit/receive control example of E PROM (M6M80012P) adaptable to the I BUS interface.

  • Page 195: E 2 Prom Functions

    APPLICATION 5.4 Example of I C-BUS interface control (M37221Mx-XXXSP/FP) 5.4.3 E PROM functions (1) Byte write Bytes are written by sending the START condition, slave address “A0 ,” sub-address (1 byte), data (1 byte), and the STOP condition from the master. Writing to the E PROM will be started after the master sends the STOP condition, that is, in synchronization with a rising edge of the SDA signal.

  • Page 196: General Flowchart

    APPLICATION 5.4 Example of I C-BUS interface control (M37221Mx-XXXSP/FP) 5.4.4 General flowchart The processing routines which controls I C-BUS devices branch to the write processing routine and the read processing routine. The data output processing routine is used as the common processing routine. (1) Write processing routine Accumulator C status register...

  • Page 197: Fig. 5.4.5 Flowchart Of Read Processing Routine

    APPLICATION 5.4 Example of I C-BUS interface control (M37221Mx-XXXSP/FP) (2) Read processing routine Accumulator C data shift register C status register Slave address Slave address C clock control register Sub-address Data (W) “A0 ” (R) “A1 ” S1D: C control register IICE: Multi-master I C interface...

  • Page 198: Fig. 5.4.6 Flowchart Of Data Output Processing Routine

    APPLICATION 5.4 Example of I C-BUS interface control (M37221Mx-XXXSP/FP) (3) Data output processing routine The data output processing routine is the common routine within the transmit/receive processing routine. Accumulator Data output C data shift register C status register TRX: Communication mode specification bit Store the number of output bytes to internal RAM Arbitration lost detecting flag PIN:...

  • Page 199: Example Of I

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) Althogh, the M37220M3-XXXSP/FP has no multi-master I C-BUS interface, it can control single-master I BUS by software. Most TV systems can be controlled in this way. This paragraph explains transmit/receive control example of a single-chip color TV signal processor (M52340SP) adaptable to the I C-BUS interface.

  • Page 200: Single-Chip Color Tv Signal Processor Function

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) 5.5.3 Single-chip color TV signal processor function (1) Status read Status is read by sending the START condition, slave address “BB .” After ACK is generated from the M52340SP, the status data is read out. After the status data is output, any acknowledge bit is not generated, but the STOP condition is sent by the master.

  • Page 201: General Flowchart

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) 5.5.4 General flowchart (1) Write processing routine The processing routine which controls I C-BUS devices branch to the write processing routine and the read processing routine. The START condition, the STOP condition and the data output processing routine are used as the common processing routine.

  • Page 202: Fig. 5.5.5 Flowchart Of Read Processing Routine

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) (2) Read processing routine (See note 1) Slave address Slave address Sub-address Data (W) “A0 ” (R) “A1 ” RAM: WRITEDATA NO ACK COUNTER Read start READ DATA COUNTER Flag: F_ACK To M52340SP ? (See note 2)

  • Page 203: Fig. 5.5.6 Flowchart Of Data Output Processing Routine

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) (3) Data output processing routine The data output, the START condition, the STOP condition, and the bus H processing routines are the common routines within the transmit/receive processing routine. RAM: WRITEDATA Data output BIT COUNTER...

  • Page 204: Fig. 5.5.7 Flowchart Of Start Condition Processing Routine

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) (4) START condition processing routine START condition (SDA) = “1” Bit 0 of port P2 direction register = “output mode” Wait 6 µ s (SCL) = “1” (SDA) = “0” Wait 6 µ...

  • Page 205: Fig. 5.5.10 Flowchart Of Data Input Processing Routine

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) (7) Data input processing routine RAM: READDATA Data intput BIT COUNTER Bit 0 of port P2 direction register = “input mode” “BIT COUNTER” = “0” (SCL) = “1” Wait 6 µ s (SDA) = “1”? Carry flag = “1”...

  • Page 206: Fig. 5.5.11 Flowchart Of Return Ack Processing Routine

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) (8) Return ACK processing routine Return ACK Bit 0 of port P2 direction register = “output mode” (SDA) = “0” Wait 6 µ s (SCL) = “1” Wait 6 µ s (SCL) = “0”...

  • Page 207: Data Setting According To Key Processing

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) 5.5.5 Data setting according to key processing Examples of the M52340SP settings, corresponding to each actual TV set key input, are described below. (1) “Power ON/OFF key” input When power supply is supplied to the M52340SP by this input, the data is set to all registers (at sub-addresses “00 ”...

  • Page 208: Table 5.5.5 Data Setting When Changing Aft State

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) (6) Data setting when changing AFT (auto fine Table 5.5.5 Data setting when changing AFT state tuning) state Sub-address Data To change the state of auto fine tuning at DEFEAT presetting CH and ordinary tuning, the bit is set as shown in Table 5.5.5.

  • Page 209: Flowchart Of Data Setting According To Key Processing

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) 5.5.6 Flowchart of data setting according to key processing Figures 5.5.13 to 5.5.15 show the flowcharts of controlling the M52340SP when there are various event inputs to the actual TV system. (1) Poweron processing by “power key“...

  • Page 210: Fig. 5.5.14 Flowchart Of "Ch Up/Down Key" Input Processing

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) (2) “CH UP/DOWN key“ input processing CH UP/DOWN To mute video and audio: MUTE (D6 at sub-address 0B )←“1” A MUTE (D6 at sub-address 01 )←“1” Related processings: •Changing CH •OSD when changing CH •Write last data to E PROM...

  • Page 211: Fig. 5.5.15 Flowchart Of "Picture Memory Switching Key" Input Processing

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) (3) Processing of “picture memory switching key“ input Picture memory switching Related processings: •Read out picture data from RAM •Changing picture data •OSD when switching picture memory •Write last data to E PROM , etc.

  • Page 212: Register Map

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) 5.5.7 Register map The M52340SP has 2 kinds of registers; the status data register and the write data registers. (1) Status data register The status data register indicates various signal state from the M52340SP side. The state is confirmed by regularly reading each bit.
  • Page 213 APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) Bit 0: Color system determination bit 0 (CONDITION) This bit indicates whether the color system is being determined or not. Figure 5.5.16 shows the state of determination, according to the bit, when AUTO (bit 5 at sub-address 06 , write data) is set to “1.”...

  • Page 214: Fig. 5.5.17 Map Of Write Data Register

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) (2) Write data register Write data register Sub-address POS/NEG DELAY ADJ A MUTE VCO ADJ TRAP 4.5/6.0 AUDIO ATT SHARPNESS DEFEAT CONTRAST AUTO TV/EXT DL TIME TINT COLOR 3.58 NTSC SECAM H PHASE BRIGHT...

  • Page 215: Table 5.5.9 Relationship Between Dfa And Dl Time

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) DELAY ADJ This adjusts the RF AGC delay point. The output level of tuner decreases when the value increase, the output level increases when the value decreases. POS/NEG This switch sets the VIF output signal to either the positive or the negative modulation signal. When “0,”...

  • Page 216: Table 5.5.10 Setting Of Color System

    APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) SHARPNESS, CONTRAST, TINT, COLOR, BRIGHT Data is set to change the picture data. Some TVs have a picture mode function (such as the movie mode, standard mode), the fixed data is set according to the mode.
  • Page 217 APPLICATION 5.5 Example of I C-BUS control by software (M37220M3-XXXSP/FP) SERSW This switch is for white balance adjustments of the TV picture in the factory. When SERSW is “0,” it is OFF; when “1,” it is ON. This switch stops horizontal oscillation. When HST is “0,” the oscillation continues; when “1,” it stops.

  • Page 218: Application Circuit Example

    APPLICATION 5.6 Application circuit example 5.6 Application circuit example 5.6.1 Application circuit example 1 M37221Mx-XXXSP/FP M52340SP TELETEXT PROM M6M80012P/22P 7220 Group User’s Manual 5-45...

  • Page 219: Application Circuit Example 2

    APPLICATION 5.6 Application circuit example 5.6.2 Application circuit example 2 M37220M3-XXXSP/FP 5-46 7220 Group User’s Manual...

  • Page 220: Chapter 6. Appendix

    C H A P T E R 6 APPENDIX 6.1 Package outlines 6.2 Termination of unused pins 6.3 Notes on use 6.4 Countermeasures against noise 6.5 Memory assignment 6.6 SFR assignment 6.7 Control registers 6.8 Ports 6.9 Machine instruction table 6.10 Instruction code table 6.11 Mask ROM ordering method 6.12 Mark specification form...

  • Page 221: Package Outline

    APPENDIX 6.1 Package outline 6.1 Package outline 7220 Group User’s Manual...

  • Page 222: Table 6.2.1 Termination Of Unused Pins

    APPENDIX 6.2 Termination of unused pins 6.2 Termination of unused pins Table 6.2.1 Termination of unused pins Input/ Termination Output M37221Mx-XXXSP/FP M37220M3-XXXSP/FP /PWM0–P0 /PWM5 /INT2/A-D4 /INT1 /OUT2 /SCL1 /SCL2 /SDA1 /SDA2 /A-D1/INT3 Set the port direction registers for the input /A-D2 mode and pull-down through a resistor.

  • Page 223: Notes On Use

    APPENDIX 6.3 Notes on use 6.3 Notes on use Notes on programming and equipping when using M37221M6-XXXSP/FP are described below. 6.3.1 Notes on processor status register (1) Initialization of processor status register The contents of processor status register (PS) Reset are undefined except the I flag (I = “1”) immediately after reset.

  • Page 224: Notes On Decimal Operation

    APPENDIX 6.3 Notes on use 6.3.2 Notes on decimal operation (1) How to execute arithmetic operation instructions in decimal operation mode To calculate in decimal notation, set the decimal operation mode flag (D) to “1” by using the Set the decimal mode flag D SED instruction, and execute the ADC and to “1”...

  • Page 225: Notes On Serial I/O

    APPENDIX 6.3 Notes on use (2) How to switch an external interrupt detection edge For the products able to switch the external interrupt detection edge, switch it as Figure 6.3.6. Clear an interrupt enable bit to “0” (interrupt disabled) Reason Switch the detection edge The interrupt circuit recognizes the switching of the detection edge as the change of external...

  • Page 226: Notes On Timer

    APPENDIX 6.3 Notes on use 6.3.5 Notes on timer When a timer value is read, “the timer value at read timing + 1” may be read. Reason Figure 6.3.8 shows the relation between timer values and their values read. Timer values are changed at the rising edge of the count source, but the values read are counted down at the falling edge of the count source.

  • Page 227: Notes On A-D Comparator

    APPENDIX 6.3 Notes on use 6.3.6 Notes on A-D comparator (1) Signal source impedance for analog input Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 µ F to 1 µ F. Further, be sure to verify the operation of application products on the user side.

  • Page 228: Notes On Input And Output Pins

    APPENDIX 6.3 Notes on use 6.3.8 Notes on input and output pins (1) Fix of a port input level in stand-by state In stand-by state for low-power dissipation, do not make input levels of an input port and an I/O port “undefined,”...

  • Page 229: Note On Multi-Master I

    APPENDIX 6.3 Notes on use 6.3.10 Note on multi-master I C-BUS interface This function is used at f(X ) = 8.0 MHz of oscillation frequency. 6.3.11 Termination of unused pins (1) Proper termination of unused pins Output ports : Open Input ports : Connect each pin to V or V...

  • Page 230: Countermeasures Against Noise

    APPENDIX 6.4 Countermeasures against noise 6.4 Countermeasures against noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.

  • Page 231: Fig.6.4.3 Wiring For Cnv

    APPENDIX 6.4 Countermeasures against noise (3) Wiring to CNVss pin Connect the CNV pin to the V pin with the shortest possible wiring. Noise Reason The processor mode of a microcomputer is influenced by a potential at the CNV pin. If a potential difference is caused by the noise between pins CNV and V...

  • Page 232: Connection Of A Bypass Capacitor Across

    APPENDIX 6.4 Countermeasures against noise 6.4.2 Connection of a bypass capacitor across line and V line Connect an approximately 0.1 µ F bypass capacitor across the V line and the V line as follows: Connect a bypass capacitor across the V Chip and the V pin at equal length.

  • Page 233: Fig.6.4.7 Wiring For Large Current Signal Line

    APPENDIX 6.4 Countermeasures against noise 6.4.4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping an oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines Microcomputer where a current larger than the tolerance of...

  • Page 234: Fig. 6.4.10 Setup For I/O Ports

    APPENDIX 6.4 Countermeasures against noise 6.4.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware> Connect a resistor of 100 Ω or more to an I/O port in series. <Software> As for an input port, read data several times by a program for checking whether input levels are equal or not.

  • Page 235: Fig. 6.4.11 Watchidog Timer By Software

    APPENDIX 6.4 Countermeasures against noise 6.4.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer.

  • Page 236: Chapter 6. Appendix

    APPENDIX 6.5 Memory assignment 6.5 Memory assignment Hexadecimal notation Decimal notation 10000 65536 0000 CRT display ROM Internal RAM (8 K bytes) for display Zero page SFR area 00C0 Special function register (384 bytes) (320 bytes) 11FFF 73727 (Refer to Figures 2. 3. 3 and 2. 3. 4) 00FF M37221M6 M37221M4...

  • Page 237: Fig. 6.5.2 Memory Assignment Of M37221M8-Xxxsp And M37221Ma-Xxxsp

    APPENDIX 6.5 Memory assignment Decimal notation Hexadecimal notation 10000 65536 0000 Internal RAM Zero page SFR area 00C0 CRT display ROM (640 bytes) (512 bytes) Special function register for display (8 K bytes) 00FF (Refer to Figures 2. 3. 3 to 2. 3. 5) 0100 M37221MA M37221M8...

  • Page 238: Fig. 6.5.3 Memory Assignment Of M37220M3-Xxxsp/Fp

    APPENDIX 6.5 Memory assignment Hexadecimal notation Decimal notation 0000 10000 65536 Internal RAM CRT display ROM (192 bytes) (4 K bytes) for display 00C0 SFR area Zero page Special function register 10FFF 69631 (256 bytes) (Refer to Figures 4.5.3 and 4.5.4) 00FF Internal RAM (64 bytes)
  • Page 239 APPENDIX 6.6 SFR assignment 6.6 SFR assignment SFR Area (addresses C0 to DF Bit allocation < > Function bit Name No function bit : Fix this bit to “0” (do not write “1”) : Fix this bit to “1” (do not write “0”) Register Bit allocation Address...

  • Page 240: After Reset And

    APPENDIX 6.6 SFR assignment State immediately after reset < > : “0” immediately after reset : Read enabled, write enabled : “1” immediately after reset RO : Read enabled, write disabled : Indeterminate immediately after reset State immediately after reset Access characteristics 7220 Group User’s Manual 6-21...

  • Page 241: Fig. 6.6.1 Sfr Assignment

    APPENDIX 6.6 SFR assignment SFR Area (addresses E0 to FF Bit allocation < > Function bit Name No function bit : Fix this bit to “0” (do not write “1”) : Fix this bit to “1” (do not write “0”) Register Bit allocation Address...
  • Page 242 APPENDIX 6.6 SFR assignment State immediately after reset < > : “0” immediately after reset : Read enabled, write enabled : “1” immediately after reset RO : Read enabled, write disabled : Indeterminate immediately after reset State immediately after reset Access characteristics 7220 Group User’s Manual 6-23...

  • Page 243: (Only M37221M8-Xxxsp And M37221Ma-Xxxsp)

    APPENDIX 6.6 SFR assignment 2 Page Register Area (addresses 217 to 21B Bit allocation < > Function bit Name No function bit : Fix this bit to “0” (do not write “1”) : Fix this bit to “1” (do not write “0”) Register Bit allocation Address...
  • Page 244 APPENDIX 6.6 SFR assignment State immediately after reset < > : “0” immediately after reset : “1” immediately after reset : Read enabled, write enabled : Undefined immediately RO : Read enabled, write disabled after reset Access characteristics State immediately after reset 7220 Group User’s Manual 6-25...

  • Page 245: Fig. 6.6.2 Sfr Assignment

    APPENDIX 6.6 SFR assignment SFR Area (addresses C0 to DF Bit allocation < > Function bit Name No function bit : Fix this bit to “0” (do not write “1”) : Fix this bit to “1” (do not write “0”) Register Bit allocation Address...
  • Page 246 APPENDIX 6.6 SFR assignment State immediately after reset < > : “0” immediately after reset : Read enabled, write enabled : “1” immediately after reset RO : Read enabled, write disabled : Undefined immediately after reset State immediately after reset Access characteristics 7220 Group User’s Manual 6-27...
  • Page 247 APPENDIX 6.6 SFR assignment SFR Area (addresses E0 to FF Bit allocation < > Function bit Name No function bit : Fix this bit to “0” (do not write “1”) : Fix this bit to “1” (do not write “0”) Register Bit allocation Address...
  • Page 248 APPENDIX 6.6 SFR assignment State immediately after reset < > : “0” immediately after reset : Read enabled, write enabled : “1” immediately after reset RO : Read enabled, write disabled : Undefined immediately after reset State immediately after reset Access characteristics 7220 Group User’s Manual 6-29...

  • Page 249: Fig. 6.7.1 Port Pi Direction Register

    APPENDIX 6.7 Control registers 6.7 Control registers Port Pi Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (Di) (i=0,1,2) [Addresses 00C1 00C3 , 00C5 Name Functions After reset R W Port Pi direction register 0 : Port Pi input mode 1 : Port Pi...

  • Page 250: Fig. 6.7.3 Port P5 Direction Register

    APPENDIX 6.7 Control registers Port P5 Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (D5) [Address 00CB Name Functions After reset R W 0, 1 Nothing is assigned. These bits are write disable bits. R —...
  • Page 251 APPENDIX 6.7 Control registers PWM Output Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 1 (PW) [Address 00D5 Name Functions After reset R W 0 : Count source supply DA, PWM count source 1 : Count source stop selection bit (PW0) 0 : DA output...

  • Page 252: Fig. 6.7.7 I C Data Shift Register

    APPENDIX 6.7 Control registers I C Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register (S0) [Address 00D7 Name Functions After reset D0 to D7 This is an 8-bit shift register to store Indeterminate receive data and write transmit data.

  • Page 253: Fig. 6.7.9 I C Status Register

    APPENDIX 6.7 Control registers C Status Register b7 b6 b5 b4 b3 b2 b1 b0 C status register (S1) [Address 00D9 Name Functions After reset R W Indeterminate R — Last receive bit (LRB) 0 : Last bit = “0 ” (See note) 1 : Last bit = “1 ”...

  • Page 254: Fig. 6.7.10 I C Control Register

    APPENDIX 6.7 Control registers C Control Register b7 b6 b5 b4 b3 b2 b1 b0 C control register (S1D : address 00DA Name Functions After reset R W Bit counter b2 b1 b0 (Number of transmit/recieve 0 : 8 bits) 1 : 7 (BC0 to BC2) 0 : 6...

  • Page 255: Fig. 6.7.11 I C Clock Contorol Register

    APPENDIX 6.7 Control registers C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 C clock control register (S2 : address 00DB Name Functions After reset R W SCL frequency control bits Setup value of Standard clock High speed (CCR0 to CCR4) CCR4–CCR0 mode...

  • Page 256: Fig. 6.7.12 Serial I/O Mode Register

    APPENDIX 6.7 Control registers Serial I/O Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O mode register (SM) [Address 00DC Name Functions After reset R W 0, 1 Internal synchronous b1 b0 clock selection bits 0: f(X (SM0, SM1) 1: f(X )/16...

  • Page 257: Fig. 6.7.14 Horizontal Position Register

    APPENDIX 6.7 Control registers DA n Conversion Register b7 b6 b5 b4 b3 b2 b1 b0 DA n conversion register (DAn) (n = 1 and 2) [Address 00DE , 00DF Name Functions After reset DA conversion set Indeterminate : 0/64Vcc bits : 1/64Vcc (DAn0–DAn5)

  • Page 258: Fig. 6.7.15 Vertical Position Register N

    APPENDIX 6.7 Control registers Vertical Position Register n b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register n (CV1,CV2) (n = 1 and 2) [Addresses 00E1 00E2 Name Functions After reset 128 steps (00 to 7F Indeterminate Vertical display start positions (CV1 : CV10 to CV16) (CV2 : CV20 to CV26) Nothing is assigned.

  • Page 259: Fig. 6.7.17 Border Selection Register

    APPENDIX 6.7 Control registers Border Selection Register b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E5 Name Functions After reset Block 1 OUT1 output 0 : Same output as character output Indeterminate (See note) border selection bit (MD10) 1 : Border output Nothing is assigned.

  • Page 260: Fig. 6.7.18 Color Register N

    APPENDIX 6.7 Control registers Color Register n b7 b6 b5 b4 b3 b2 b1 b0 Color register n (CO0 to CO3) (n = 0 to 3) [Addresses 00E6 to 00E9 Name Functions After reset R W Nothing is assigned. This bit is a write disable bit. R —...

  • Page 261: Fig. 6.7.19 Crt Control Register

    APPENDIX 6.7 Control registers CRT Control Register b7 b6 b5 b4 b3 b2 b1 b0 CRT control register (CC) [Address 00EA Functions After reset R W Name 0 : All-blocks display off All-blocks display control 1 : All-blocks display on bit (Note 1) (CC0) Block 1 display control bit 0 : Block 1 display off...

  • Page 262: Fig. 6.7.20 Crt Port Control Register

    APPENDIX 6.7 Control registers CRT Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 CRT port control register (CRTP) [Address 00EC Name Functions After reset R W input polarity 0 : Positive polarity SYNC 1 : Negative polarity switch bit (HSYC) 0 : Positive polarity input polarity...

  • Page 263: Fig. 6.7.21 Crt Clock Selection Register

    APPENDIX 6.7 Control registers CRT Clock Selection Register b7 b6 b5 b4 b3 b2 b1 b0 CRT clock selection register (CK) [Address 00ED Name Functions After reset R W Functions 0, 1 CRT clock selection bits The clock for display is supplied by connecting RC (CK0,CK1) or LC across the pins OSC1 and OSC2.
  • Page 264 APPENDIX 6.7 Control registers A-D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (AD1) [Address 00EE Name Functions After reset R W Analog input pin selection b2 b1 b0 bits 0 : A- D1 (ADM0, ADM1, ADM2) 1 : A-D2 0 : A-D3...

  • Page 265: Fig. 6.7.24 Timer 12 Mode Register

    APPENDIX 6.7 Control registers Timer 12 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Timer 12 mode register (T12M) [Address 00F4 Name Functions After reset Timer 1 count source 0: f(X )/16 selection bit (T12M0) 1: f(X )/4096 0: Internal clock Timer 2 count source 1: External clock from...

  • Page 266: Fig. 6.7.25 Timer 34 Mode Register

    APPENDIX 6.7 Control registers Timer 34 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M) [Address 00F5 Name Functions After reset R W Timer 3 count source 0: f(X )/16 selection bit (T34M0) 1: External clock 0: Timer 3 overflow Timer 4 internal count 1: f(X...

  • Page 267: Fig. 6.7.27 Cpu Mode Register

    APPENDIX 6.7 Control registers CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) (CM) [Address 00FB Name Functions After reset Fix these bits to “0.” 0, 1 0: 0 page Stack page selection (Note) 1: 1 page bit (CM2) Fix these bits to “1.”...
  • Page 268 APPENDIX 6.7 Control registers Interrupt Request Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address 00FD Name Functions After reset R W 0 INT1 interrupt 0 : No interrupt request issued request bit (ITIR) 1 : Interrupt request issued 1 INT2 interrupt 0 : No interrupt request issued...

  • Page 269: Fig. 6.7.32 Rom Correction Enable Register

    APPENDIX 6.7 Control registers Interrupt Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Interrupt control register 2 (ICON2) [Address 00FF Name Functions After reset R W 0 INT1 interrupt 0 : Interrupt disabled enable bit (IT1E) 1 : Interrupt enabled 1 INT2 interrupt enable 0 : Interrupt disabled...

  • Page 270: Fig. 6.8.1 I/O Pin Block Diagram (1)

    APPENDIX 6.8 Ports 6.8 Ports /PWM0–P0 /PWM5, P3 N-channel open-drain output Direction register Port latch Data bus M37221M4-XXXSP, M37221M6-XXXSP/FP, M37221M8-XXXSP, M37221MA-XXXSP /OUT2, P1 /SCL1, P1 /SCL2, P1 /SDA1, P1 /SDA2, P1 /A-D1/INT3, P1 /A-D2, P1 /A-D3, , P2 , P2 , P2 /TIM3, P2 /TIM2, P2...

  • Page 271: Fig. 6.8.2 I/O Pin Block Diagram (2)

    APPENDIX 6.8 Ports /OSC1, P3 Input Internal circuit M37221M4-XXXSP, M37221M6-XXXSP/FP, M37221M8-XXXSP, M37221MA-XXXSP D-A, P5 /R, P5 /G, P5 /B, P5 /OUT1 M37220M3-XXXSP/FP D-A, P5 /R, P5 /G, P5 /B, P5 /OUT CMOS output Internal circuit SYNC SYNC Schmidt input SYNC SYNC indicates a pin.
  • Page 272 APPENDIX 6.9 Machine instruction table 6.9 Machine instruction table Machine instructions 7220 Group User’s Manual 6-53...
  • Page 273 APPENDIX 6.9 Machine instruction table 6-54 7220 Group User’s Manual...
  • Page 274 APPENDIX 6.9 Machine instruction table 7220 Group User’s Manual 6-55...
  • Page 275 APPENDIX 6.9 Machine instruction table 6-56 7220 Group User’s Manual...
  • Page 276 APPENDIX 6.9 Machine instruction table 7220 Group User’s Manual 6-57...
  • Page 277 APPENDIX 6.9 Machine instruction table 6-58 7220 Group User’s Manual...
  • Page 278 APPENDIX 6.9 Machine instruction table 7220 Group User’s Manual 6-59...
  • Page 279 APPENDIX 6.9 Machine instruction table 6-60 7220 Group User’s Manual...
  • Page 280 APPENDIX 6.9 Machine instruction table 7220 Group User’s Manual 6-61...
  • Page 281 APPENDIX 6.9 Machine instruction table 6-62 7220 Group User’s Manual...
  • Page 282 APPENDIX 6.10 Instruction code table 6.10 Instruction code table –D 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Hexadecimal notation –D 0000 IND,X 0,ZP 0,ZP IND,X ZP,IND 0001 IND,Y ZP,X ZP,X 0,ZP ABS,Y ABS,X ABS,X...
  • Page 283 APPENDIX 6.11 Mask ROM ordering method 6.11 Mask ROM ordering method When placing an order, please submit the information described below. M37221M4-XXXSP Mask ROM Ordering Confirmation Form..1 set (Please use the pages P6-65 to P6-67) M27221M8-XXXSP Mask ROM Ordering Confirmation Form..1 set (Please use the pages P6-68 to P6-70) M37221M6-XXXSP/FP Mask ROM Ordering Confirmation Form..1 set (Please use the pages P6-71 to P6-73)
  • Page 284 APPENDIX 6.11 Mask ROM ordering method GZZ–SH10–10B < 59B0 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M4-XXXSP MITSUBISHI ELECTRIC Date : Section head Supervisor signature signature Note : Please fill in all items marked Submitted by Supervisor Company name...
  • Page 285 APPENDIX 6.11 Mask ROM ordering method GZZ–SH10–10B <59B0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M4-XXXSP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 0000 to 000F store the product name, and addresses 10000 to 11FFF store the character pattern.
  • Page 286 APPENDIX 6.11 Mask ROM ordering method GZZ–SH10–10B< 59B0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M4-XXXSP MITSUBISHI ELECTRIC The structure of character ROM (divided of 12 16 dots font) Example (Note) Character code Write the character code “00 ”...
  • Page 287 APPENDIX 6.11 Mask ROM ordering method GZZ–SH11–58B < 72A0 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M8-XXXSP MITSUBISHI ELECTRIC Date : Section head Supervisor signature signature Note : Please fill in all items marked Submitted by Supervisor Company name...
  • Page 288 APPENDIX 6.11 Mask ROM ordering method GZZ–SH11–58B <72A0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M8-XXXSP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 0000 to 000F store the product name, and addresses 10000 to 11FFF store the character pattern.
  • Page 289 APPENDIX 6.11 Mask ROM ordering method GZZ–SH11–58B< 72A0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M8-XXXSP MITSUBISHI ELECTRIC The structure of character ROM (divided of 12 16 dots font) Example (Note) Character code Write the character code “00 ”...
  • Page 290 APPENDIX 6.11 Mask ROM ordering method GZZ–SH09–46B < 52C0 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M6-XXXSP/FP Date : MITSUBISHI ELECTRIC Section head Supervisor signature signature Note : Please fill in all items marked Submitted by Supervisor Company name...
  • Page 291 APPENDIX 6.11 Mask ROM ordering method GZZ–SH09–46B <52C0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M6-XXXSP/FP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 0000 to 000F store the product name, and addresses 10000 to 11FFF store the character pattern.
  • Page 292 APPENDIX 6.11 Mask ROM ordering method GZZ–SH09–46B< 52C0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M6-XXXSP/FP MITSUBISHI ELECTRIC The structure of character ROM (divided of 12 16 dots font) Example (Note) Character code Write the character code “00 ”...
  • Page 293 APPENDIX 6.11 Mask ROM ordering method GZZ–SH10–46B < 5ZA0 > Mask ROM number SERIES MELPS 740 MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221MA-XXXSP Date : MITSUBISHI ELECTRIC Section head Supervisor signature signature Note : Please fill in all items marked Submitted by Supervisor Company...
  • Page 294 APPENDIX 6.11 Mask ROM ordering method GZZ–SH10–46B <5ZA0 > SERIES MELPS 740 MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221MA-XXXSP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 0000 to 000F store the product name, and addresses 10000 to 11FFF store the character pattern.
  • Page 295 APPENDIX 6.11 Mask ROM ordering method GZZ–SH10–46B< 5ZA0 > SERIES MELPS 740 MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221MA-XXXSP MITSUBISHI ELECTRIC The structure of character ROM (divided of 12 16 dots font) Example (Note) Character code Write the character code “00 ”...
  • Page 296 APPENDIX 6.11 Mask ROM ordering method GZZ–SH09–72B < 56B0 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37220M3-XXXSP Date : MITSUBISHI ELECTRIC Section head Supervisor signature signature Note : Please fill in all items marked Supervisor Submitted by Company name...
  • Page 297 APPENDIX 6.11 Mask ROM ordering method GZZ–SH09–72B <56B0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37220M3-XXXSP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 0000 to 000F store the product name, and addresses 10000 to 10FFF store the character pattern.
  • Page 298 APPENDIX 6.11 Mask ROM ordering method GZZ–SH09–72B< 56B0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37220M3-XXXSP MITSUBISHI ELECTRIC The structure of character ROM (divided of 12 16 dots font) Example Character code “1A ” Character Character ROM1 ROM2 Example 101A0 Example...
  • Page 299 APPENDIX 6.12 Mark specification form 6.12 Mark specification form 42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM 6-80 7220 Group User’s Manual...
  • Page 300 APPENDIX 6.12 Mark specification form 42P2R-A (42-PIN SHRINK SOP) MARK SPECIFICATION FORM 7220 Group User’s Manual 6-81...
  • Page 301 MITSUBISHI SEMICONDUCTORS USER’S MANUAL 7220 Group Jul. First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
  • Page 302 User’s Manual 7220 Group New publication, effective Jul. 1997. © 1997 MITSUBISHI ELECTRIC CORPORATION. Specifications subject to change without notice.
  • Page 303 REVISION DESCRIPTION LIST 7220 GROUP USER'S MANUAL Rev. Rev. Revision Description date 9708 First Edition 971130 Information about copywright note, revision number, release date added (last page). (1/1)

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