Renesas 7700 FAMILY User Manual page 70

4.7 Sequence from acceptance of interrupt request to execution of interrupt routine
Interrupt request is accepted.
Interrupt request occurs.
Instruction
1
Time from the occurrence of an interrupt request until the completion of executing an instruction
which is being executed at the occurrence.
Time from the instruction next to
being done at the end of priority detection
Note : At this time, interrupt priority detection starts.
Time required to execute the INTACK sequence (15 cycles of φ at minimum)
Fig. 4.7.1 Sequence from acceptance of interrupt request to execution of interrupt routine
When 2 access in low-speed running and stack pointer(S)'s content is even
φ
φ
CPU
A
Undefined
H(CPU)
A A Undefined
M L(CPU)
DATA
Undefined
H(CPU)
Undefined
DATA
L(CPU)
E
[S] : Contents of stack pointer (S)
FFXX : Vector address
16
Fig. 4.7.2 INTACK sequence timing (at minimum)
@
Instruction
INTACK sequence
2
Interrupt response time
(Note) until the completion of executing an instruction which is
00 00 00
0000 0000 0000
IPL
Vector address
(Low order)
7751 Group User's Manual
@
Instructions in interrupt routine
@ : Duration for detecting interrupt priority
level
00 00
[S] [S]–2
PC
H
PG PC
L
INTACK sequence
INTERRUPTS
Time
00 00 00
[S]–4 [S]–4
FFXX
16
AD
PS
H
AD
PS
L
00
AD AD
M L
'
Next instruction
M
Next instruction
L
4–15