Interrupt Priority Level Detection Circuit - Renesas 7700 FAMILY User Manual

4.5 Interrupt priority level detection circuit

The interrupt priority level detection circuit selects the interrupt having the highest priority level when more
than one interrupt request occurs at the same sampling timing. Figure 4.5.1 shows the interrupt priority level
detection circuit.
Interrupt priority level
Interrupt
disable flag (I)
Fig. 4.5.1 Interrupt priority level detection circuit
Level 0 (initial value)
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
The highest priority level interrupt
Watchdog timer interrupt
Reset
7751 Group User's Manual
4.5 Interrupt priority level detection circuit
Interrupt priority level
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
Processor interrupt priority level
Accepting of interrupt request
INTERRUPTS
INT
2
INT
1
INT
0
IPL
4–11