Renesas 7700 FAMILY User Manual page 428

Read command
Figure 19.1.5 shows the read command execution timing.
The command code is latched into the internal command latch at the rising edge of the WE signal
by inputting the control signals and the command code "00
The data of the specified address (input address) is output to an external by inputting the address
and control signals in the second cycle.
The read command code which is latched into the command latch is retained until any other
command code is latched into the command latch. Accordingly, when the second cycle input over
again after the read command code is input in the first cycle, the read command is executed over
again.
The read command code is latched into the command latch after power–on.
A –A
0 16
CE
OE
WE
Floating
D –D
0 7
V H
PP
V
PP
V L
PP
Fig. 19.1.5 Read command execution timing
Note: When executing any command other than the read command, input the command code
(input from the first cycle) each time the execution.
FLASH MEMORY VERSION
t
WC
t
RRW
t
CH
t
CS
t
WP
t
DS
Floating
00
16
t
DH
t
VSC
First cycle
7751 Group User's Manual
19.1 Parallel input/output mode
" in the first cycle.
16
Read address
t
RC
t
WRR
t
a
(CE)
t
a
(OE)
t
OLZ
t
CLZ
t
a
(AD)
Second cycle
___
t
DF
t
OH
Floating
Data
Read data output
19–11