Renesas 7700 FAMILY User Manual page 480

Processor mode register 1
b7 b6 b5 b4 b3 b2
0 0
b1 b0
Processor mode register 1 (Address 5F
0 0
Bit
1, 0 Fix these bits to "0."
Clock source for peripheral
2
devices select bit
CPU running speed select bit
3
Bus cycle select bits
4
5
Fix these bits to "0."
7, 6
Note: Fix this bit to "0" when f(X
7751 Group User's Manual
)
16
Bit name
0 : divided by 2
(Note)
1 :
0 : High-speed running
1 : Low-speed running
(Note)
In high-speed running
b5 b4
0 0 : 5 access in high-speed running
0 1 : 4 access in high-speed running
1 0 : 3 access in high-speed running
1 1 : Not selected
In low-speed running
b5 b4
0 0 : Not selected
0 1 : 4 access in low-speed running
1 0 : 3 access in low-speed running
1 1 : 2 access in low-speed running
) > 25 MHz.
IN
APPENDIX
Appendix 3. Control registers
Functions
At reset RW
RW
0
RW
0
0 RW
0
RW
0
RW
RW
0
20–29