Renesas 7700 FAMILY User Manual page 84

5.2 Block description
Figure 5.2.1 shows the block diagram of Timer A. Explanation of relevant registers to Timer A is described
below.
f /f
2 4
f /f
16 32
f /f
64 128
f /f
512 1024
Polarity
TAi
IN
switching
TAi
OUT
Fig. 5.2.1 Block diagram of Timer A
Count source
select bits
Timer mode
One-shot pulse mode
PWM mode
Timer mode
(Gate function)
Event counter mode
Trigger
7751 Group User's Manual
Data bus (odd)
Data bus (even)
(Low-order 8 bits)
Timer Ai reload register (16)
Timer Ai counter (16)
Count start bit
Down-count
Up-down bit
Pulse output
function select bit
Toggle
F.F.
TIMER A
5.2 Block description
(High-order 8 bits)
Up-count/down-count
switching
(Always down-count except
for event counter mode)
Timer Ai
interrupt
request bit
5–3