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APPLICATIONS
17.1 Memory expansion
M37751
CNV
SS
A
–A
1
7
BYTE
A
/D
–
8
8
A
/D
15
15
A
/D
16
0
ALE
D
–D
1
7
E
R/W
X
X
IN
OUT
40 MHz
Fig. 17.1.27 Example of ROM expansion (maximum model at high-speed running)
<When reading>
E, OE
A
/D
–A
/D
8
8
15
15
A
/D
16
0
R/W
CE
External ROM
data output
Fig. 17.1.28 Timing chart for ROM expansion example (maximum model at high-speed running)
17–32
M5M27C102K-12
Address bus
A
–A
1
16
1
AC573
D
Q
A
–A
8
15
LE
AC573
A
16
D
Q
LE
Data bus
D
–D
0
15
2
AC04
Circuit condition : 5 access in high-speed running
40 (min.)
A
45 (min.)
t
su
(P0A/P1A/P2A-P1D/P2D)
t
+AC573 (t
a
(AD)
AC04 (t
PHL
7751 Group User's Manual
1: Use the elements of which propagation
delay time is within 30 ns.
2: Use the elements of which propagation
delay time is within 35 ns.
A
A
–
0
15
0000
0080
0880
D
D
–
0
15
OE
CE
1FFFF
125 (min.)
5 (max.)
= 150
/t
)
PHL
PLH
)
AC04 (t
t
a
(OE)
t
a
(CE)
Memory map
16
SFR area
16
Internal RAM
area
16
External ROM
area
(M5M27C102K)
16
15 (min.)
A
15 (max.)
)
PLH
15 (max.)
( Kit guaranteed )
D
≥ 30
t
su
(P1D/P2D-E)
(Unit : ns)
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