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INPUT/OUTPUT PINS
3.1 Programmable I/O ports
Figures 3.1.4 and 3.1.5 show the port peripheral circuits.
[Inside dotted-line not included]
Ports P0
to P0
, P1
to P1
0
7
0
P3
to P3
, P4
to P4
0
3
3
[Inside dotted-line included]
Ports P4
, P4
, P4
, P5
0
1
7
P5
/TA2
, P5
/TA3
5
IN
7
P6
/INT
to P6
/INT
2
0
4
P8
/RxD
, P8
/RxD
2
0
6
(There is no hysteresis for P8
[Inside dotted-line not included. ]
Ports P4
/
, P8
/TxD
2
1
3
0
[Inside dotted-line included. ]
Ports P5
/TA0
, P5
/TA1
0
OUT
2
P5
/TA3
, P6
/TA4
6
OUT
0
[ Inside dotted-line not included]
Ports P7
/AN
to P7
/AN
0
0
6
[ Inside dotted-line included]
Port P7
/AN
/AD
7
7
TRG
Fig. 3.1.4 Port peripheral circuits (1)
3–6
, P2
to P2
,
7
0
7
6
Data bus
/TA0
, P5
/TA1
,
1
IN
3
IN
, P6
/TA4
,
IN
1
IN
, P6
/TB0
to P6
/TB2
,
2
5
IN
7
IN
1
/RxD
and P8
/RxD
2
0
6
, P8
/TxD
7
1
Data bus
, P5
/TA2
,
OUT
4
OUT
OUT
6
Data bus
7751 Group User's Manual
Direction register
Port latch
.)
1
Direction register
Port latch
Direction register
Port latch
Analog input
"1"
Output
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