Renesas 7700 FAMILY User Manual page 214

Mitsubishi 16-bit single-chip microcomputer
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(2) Trigger select bit (bit 5)
This bit is used to select the source of trigger occurrence. (Refer to "(3) A-D conversion start bit.")
(3) A-D conversion start bit (bit 6)
When internal trigger is selected
Setting this bit to "1" generates a trigger, causing the A-D converter to start operating. Clearing
this bit to "0" causes the A-D converter to stop operating.
In the one-shot mode or single sweep mode, this bit is cleared to "0" after the operation is
completed. In the repeat mode, repeat sweep mode 0 or repeat sweep mode 1, the A-D converter
continues operating until this bit is cleared to "0" by software.
When external trigger is selected
______
When the
AD
A-D converter to start operating. The A-D converter stops when this bit is cleared to "0."
In the one-shot mode or single sweep mode, this bit remains set to "1" even after the operation
is completed. In the repeat mode, repeat sweep mode 0 or repeat sweep mode 1, the A-D
converter continues operating until this bit is cleared to "0" by software.
(4) A-D conversion frequency (φ
The operating time of the A-D converter varies depending on the selected operating clock (φ
this bit and the A-D conversion frequency (φ
8.2.3) as listed in Table 8.2.3.
Since the A-D converter's comparator consists of capacity coupling amplifiers, keep that φ
kHz during A-D conversion.
Table 8.2.1 Time for performance to one analog input pin (unit: µ s)
Clock source for peripheral devices select bit
A-D conversion frequency (φ
A-D conversion frequency (φ
φ
AD
8-bit resolution
f(X
) = 25 MHz
IN
10-bit resolution
8-bit resolution
f(X
) = 40 MHz
IN
10-bit resolution
pin level goes from "H" to "L" with this bit = "1," a trigger occurs, causing the
TRG
) select bit 0 (bit 7)
AD
) select bit 1
0
AD
) select bit 0
0
AD
f
divided by 4
4
31.36
37.76
19.60
23.60
7751 Group User's Manual
) select bit 1 (bit 4 at address 1F
AD
0
0
1
1
0
f
divided by 2
f
4
4
15.68
7.84
18.88
9.44
9.80
4.90
11.80
5.90
A-D CONVERTER
8.2 Block description
; refer to Figure
16
1
0
0
0
1
f
divided by 4
f
divided by 2
2
2
15.68
7.84
18.88
9.44
–––
–––
–––
–––
) by
AD
≥ 250
AD
1
0
f
2
3.92
4.72
–––
–––
8–5

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